參數(shù)資料
型號: XC6SLX100T-2FG676I
廠商: Xilinx Inc
文件頁數(shù): 75/89頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 6 676FGGBGA
標準包裝: 40
系列: Spartan® 6 LXT
LAB/CLB數(shù): 7911
邏輯元件/單元數(shù): 101261
RAM 位總計: 4939776
輸入/輸出數(shù): 376
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 676-BGA
供應商設備封裝: 676-FBGA(27x27)
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
77
Table 75: Global Clock Setup and Hold With PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
Units
-3
-3N
-2
-1L
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1)
TPSPLL0/ TPHPLL0
No Delay Global Clock and IFF(2)
with PLL in Source-Synchronous
Mode
XC6SLX4
0.47/1.08
N/A
0.47/1.60
1.15/1.68
ns
XC6SLX9
0.47/1.08
0.47/1.35
0.47/1.60
1.15/1.68
ns
XC6SLX16
0.37/0.75
0.37/0.82
0.51/0.94
0.57/1.31
ns
XC6SLX25
0.69/1.06
1.86/1.67
ns
XC6SLX25T
0.69/1.06
N/A
ns
XC6SLX45
0.57/1.05
0.65/1.10
0.65/1.18
1.02/1.65
ns
XC6SLX45T
0.57/1.06
0.65/1.10
0.65/1.18
N/A
ns
XC6SLX75
0.86/1.04
0.87/1.04
0.90/1.04
1.34/1.55
ns
XC6SLX75T
0.86/1.04
0.87/1.04
0.90/1.04
N/A
ns
XC6SLX100
0.53/1.13
0.54/1.13
0.55/1.13
0.89/2.39
ns
XC6SLX100T
0.53/1.13
0.54/1.13
0.55/1.13
N/A
ns
XC6SLX150
0.50/1.31
0.51/1.31
0.52/1.31
1.02/1.72
ns
XC6SLX150T
0.50/1.31
0.51/1.31
0.52/1.31
N/A
ns
XA6SLX4
0.71/0.93
N/A
0.62/1.47
N/A
ns
XA6SLX9
0.71/0.93
N/A
0.62/1.47
N/A
ns
XA6SLX16
0.92/0.69
N/A
0.63/0.82
N/A
ns
XA6SLX25
0.99/0.94
N/A
0.96/0.94
N/A
ns
XA6SLX25T
0.99/0.94
N/A
1.04/0.94
N/A
ns
XA6SLX45
0.63/1.02
N/A
0.72/1.05
N/A
ns
XA6SLX45T
0.63/1.02
N/A
0.72/1.05
N/A
ns
XA6SLX75
0.88/0.89
N/A
1.02/0.89
N/A
ns
XA6SLX75T
0.88/0.89
N/A
1.02/0.89
N/A
ns
XA6SLX100
N/A
1.25/0.96
N/A
ns
XQ6SLX75
N/A
1.02/0.89
1.34/1.55
ns
XQ6SLX75T
0.88/0.89
N/A
1.02/0.89
N/A
ns
XQ6SLX150
N/A
0.63/1.19
1.02/1.72
ns
XQ6SLX150T
0.60/1.19
N/A
0.63/1.19
N/A
ns
Notes:
1.
Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock
input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using
the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2.
IFF = Input Flip-Flop or Latch
3.
Use IBIS to determine any duty-cycle distortion incurred using various standards.
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