參數(shù)資料
型號(hào)： XC3142L-3TQ144C
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 144 CLBS, 2000 GATES, 270 MHz, PQFP144
封裝： PLASTIC, TQFP-144
文件頁(yè)數(shù)： 39/76頁(yè)
文件大?。?/td> 731K
代理商： XC3142L-3TQ144C
R
November 9, 1998 (Version 3.1)
7-41
XC3000 Series Field Programmable Gate Arrays
7
XC3000A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3000A Operating Conditions
Note:
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per
°
C.
XC3000A DC Characteristics Over Operating Conditions
Notes:
1. With no output current loads, no active input or Longline pull-up resistors, all package pins at V
CC
or GND, and the FPGA
device configured with a tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed
100 mA per V
pin. The number of ground pins varies from the XC3020A to the XC3090A.
3. Not tested. Allow an undriven pin to float High. For any other purposes use an external pull-up.
Symbol
V
CC
Description
Min
4.75
4.5
2.0
0
70%
0
Max
5.25
5.5
V
CC
0.8
100%
20%
250
Units
V
V
V
V
V
CC
V
CC
ns
V
IHT
V
ILT
V
IHC
V
ILC
T
IN
Supply voltage relative to GND Commercial 0
°
C to +85
°
C junction
Supply voltage relative to GND Industrial -40
°
C to +100
°
C junction
High-level input voltage — TTL configuration
Low-level input voltage — TTL configuration
High-level input voltage — CMOS configuration
Low-level input voltage — CMOS configuration
Input signal transition time
Symbol
V
OH
V
OL
V
OH
V
OL
V
CCPD
I
CCPD
Description
Min
3.86
Max
Units
V
V
V
V
V
High-level output voltage (@ I
OH
= –4.0 mA, V
CC
min)
Low-level output voltage (@ I
OL
= 4.0 mA, V
CC
min)
High-level output voltage (@ I
OH
= –4.0 mA, V
CC
min)
Low-level output voltage (@ I
OL
= 4.0 mA, V
CC
min)
Power-down supply voltage (PWRDWN must be Low)
Power-down supply current
(V
CC(MAX)
@ T
MAX
)
Commercial
0.40
Industrial
3.76
0.40
2.30
3020A
3030A
3042A
3064A
3090A
100
160
240
340
500
μ
A
μ
A
μ
A
μ
A
μ
A
I
CCO
Quiescent FPGA supply current in addition to I
CCPD
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
Input Leakage Current
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
Pad pull-up (when selected) @ V
IN
= 0 V
3
Horizontal Longline pull-up (when selected) @ logic Low
500
10
+10
μ
A
μ
A
μ
A
I
IL
–10
C
IN
10
15
pF
pF
16
20
0.17
3.4
pF
pF
mA
mA
I
RIN
I
RLL
0.02
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