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參數(shù)資料
| 型號(hào)： | XC3142L-3TQ144C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 144 CLBS, 2000 GATES, 270 MHz, PQFP144 |
| 封裝： | PLASTIC, TQFP-144 |
| 文件頁(yè)數(shù)： | 32/76頁(yè) |
| 文件大?。?/td> | 731K |
| 代理商： | XC3142L-3TQ144C |
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R
XC3000 Series Field Programmable Gate Arrays
7-34
November 9, 1998 (Version 3.1)
General XC3000 Series Switching Characteristics
Notes:
1. At power-up, V
CC
must rise from 2.0 V to V
CC
min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or a
non-monotonically rising V
may require a >1-
μ
s High level on RESET, followed by a >6-
μ
s Low level on RESET and D/P
after Vcc has reached 4.0 V (2.5 V for XC3000L).
2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The
specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration.
3. PWRDWN transitions must occur while V
CC
>4.0 V(2.5 V for XC3000L).
4 T
MRW
2 T
MR
3 T
RM
5 T
PGW
6 T
PGI
Clear State
Configuration State
User State
Note 3
V
CCPD
X5387
RESET
M0/M1/M2
DONE/PROG
INIT
(Output)
PWRDWN
V
CC
(Valid)
Description
M0, M1, M2 setup time required
M0, M1, M2 hold time required
RESET Width (Low) req. for Abort
Width (Low) required for Re-config.
INIT response after D/P is pulled Low
Power Down V
CC
Symbol
Min
1
4.5
6
6
Max
Units
μ
s
μ
s
μ
s
μ
s
μ
s
V
RESET (2)
2
3
4
5
6
T
MR
T
RM
T
MRW
T
PGW
T
PGI
V
CCPD
DONE/PROG
7
PWRDWN (3)
2.3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3142L-3VQ160C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
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| XC3142-PG841PH | 制造商:Xilinx 功能描述: |
| XC3142-PG84CPH | 制造商:Xilinx 功能描述: |
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