- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374980 > XC3090 (Xilinx, Inc.) Logic Cell Array Families PDF資料下載
參數(shù)資料
| 型號： | XC3090 |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Logic Cell Array Families |
| 中文描述： | 家庭邏輯單元陣列 |
| 文件頁數(shù)： | 7/50頁 |
| 文件大?。?/td> | 474K |
| 代理商： | XC3090 |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
2-109
Figure 4.
Configurable Logic Block.
Each CLB includes a combinatorial logic section, two flip-flops and a program
memory controlled multiplexer selection of function. It has.
five logic variable inputs A, B, C, D, and E
a direct data in DI
an enable clock EC
a clock (invertible) K
an asynchronous direct RESET RD
two outputs X and Y
Configurable Logic Block
The array of CLBs provides the functional elements from
which the user’s logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of IOBs. The
XC3020 has 64 such blocks arranged in 8 rows and 8
columns. The XACT development system is used to com-
pile the configuration data which is to be loaded into the
internal configuration memory to define the operation and
interconnection of each block. User definition of CLBs and
their interconnecting networks may be done by automatic
translation from a schematic-capture logic diagram or
optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 4. There are:
five logic inputs (A, B, C, D and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from
the function F or G outputs of the combinatorial logic, or the
block input, DI. Both flip-flops in each CLB share the
Q
COMBINATORIAL
FUNCTION
LOGIC
VARIABLES
D
RD
G
F
DIN
G
F
QX
QY
DIN
G
F
G
QY
QX
F
Q
D
RD
ENABLE CLOCK
CLOCK
DIRECT
RESET
1 (ENABLE)
A
B
C
D
E
DI
EC
K
RD
Y
X
X3032
0 (INHIBIT)
(GLOBAL RESET)
CLB OUTPUTS
DATA IN
0
1
0
MUX
1
MUX
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XC3100 | Logic Cell Array Families |
| XC3042A-6PC84C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3042A-7PC84C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3190A-1PP175C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| XC3120A-1PQ100C | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC3090-100CB164B | 制造商:Xilinx 功能描述: |
| XC3090-100CB164C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC3090-100CB164M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| XC3090-100CQ164C | 制造商:Xilinx 功能描述:Field-Programmable Gate Array, 320 Cell, 164 Pin, Ceramic, Quad CERPAK |
| XC3090-100PC84C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。