參數(shù)資料
型號(hào)： XC3090
廠商： Xilinx, Inc.
英文描述： Logic Cell Array Families
中文描述： 家庭邏輯單元陣列
文件頁(yè)數(shù)： 26/50頁(yè)
文件大?。?/td> 474K
代理商： XC3090
XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
2-128
Peripheral Mode
X3031
ADDRESS
BUS
DATA
BUS
D0–7
ADDRESS
DECODE
LOGIC
CS0
.
RDY/BUSY
WS
RESET
.
OTHER
I/O PINS
D0–7
CCLK
DOUT
M2
HDC
LDC
LCA
GENERAL-
PURPOSE
USER I/O
PINS
D/P
M0
M1 PWR
DWN
+5 V
CS2
CS1
CONTROL
SIGNALS
8
INIT
REPROGRAM
+5 V
5 k‰
*
IF READBACK IS
ACTIVATED, A
5-k‰ RESISTOR IS
REQUIRED IN SERIES
WITH M1
*
OPTIONAL
DAISY-CHAINED
LCAs WITH DIFFERENT
CONFIGURATIONS
OC
Figure 23.
Peripheral Mode.
Peripheral mode uses the trailing edge of the logic AND
condition of the CS0, CS1, CS2, and WS inputs to accept
byte-wide data from a microprocessor bus. In the lead LCA
device, this data is loaded into a double-buffered UART-
like parallel-to-serial converter and is serially shifted into
the internal logic. The lead LCA device presents the
preamble data (and all data that overflows the lead device)
on the DOUT pin.
The Ready/Busy output from the lead LCA device acts as
a handshake signal to the microprocessor. RDY/BUSY
goes Low when a byte has been received, and goes High
again when the byte-wide input buffer has transferred its
information into the shift register, and the buffer is ready to
receive new data. The length of the BUSY signal depends
on the activity in the UART. If the shift register had been
empty when the new byte was received, the BUSY signal
lasts for only two CCLK periods. If the shift register was still
full when the new byte was received, the BUSY signal can
be as long as nine CCLK periods.
Note that after the last byte has been entered, only seven
of its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
相關(guān)PDF資料
PDF描述
XC3100 Logic Cell Array Families
XC3042A-6PC84C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3042A-7PC84C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3190A-1PP175C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3120A-1PQ100C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3090-100CB164B 制造商:Xilinx 功能描述:
XC3090-100CB164C 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA)
XC3090-100CB164M 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA)
XC3090-100CQ164C 制造商:Xilinx 功能描述:Field-Programmable Gate Array, 320 Cell, 164 Pin, Ceramic, Quad CERPAK
XC3090-100PC84C 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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