參數(shù)資料
型號： XC3064L-8TQ144C
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 224 CLBS, 4000 GATES, 80 MHz, PQFP144
封裝： PLASTIC, TQFP-144
文件頁數(shù)： 65/76頁
文件大?。?/td> 731K
代理商： XC3064L-8TQ144C
R
November 9, 1998 (Version 3.1)
7-67
XC3000 Series Field Programmable Gate Arrays
7
XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the
118 pads on the XC3042A (and 84 of the 98 pads on the XC3030A) that are connected to the 84 package pins. Ten pads,
indicated by an asterisk, do not exist on the XC3020A, which has 74 pads; therefore the corresponding pins on the 84-pin
packages have no connections to an XC3020A. Six pads on the XC3020A and 16 pads on the XC3030A, indicated by a
dash (—) in the 68 PLCC column, have no connection to the 68 PLCC, but are connected to the 84-pin packages.
68 PLCC
XC3020A, XC3030A,
XC3042A
PWRDN
TCLKIN-I/O
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M1-RDATA
M0-RTRIG
M2-I/O
HDC-I/O
I/O
LDC-I/O
I/O
I/O*
I/O
I/O
I/O*
INIT-I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O*
I/O*
I/O
XTL2(IN)-I/O
84 PLCC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
68 PLCC
XC3020A, XC3030A,
XC3042A
RESET
DONE-PG
D7-I/O
XTL1(OUT)-BCLKIN-I/O
D6-I/O
I/O
D5-I/O
CS0-I/O
D4-I/O
I/O
VCC
D3-I/O
CS1-I/O
D2-I/O
I/O
I/O*
D1-I/O
RDY/BUSY-RCLK-I/O
D0-DIN-I/O
DOUT-I/O
CCLK
A0-WS-I/O
A1-CS2-I/O
A2-I/O
A3-I/O
I/O*
I/O*
A15-I/O
A4-I/O
A14-I/O
A5-I/O
GND
A13-I/O
A6-I/O
A12-I/O
A7-I/O
I/O*
I/O*
A11-I/O
A8-I/O
A10-I/O
A9-I/O
84 PLCC
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
2
3
4
5
6
7
8
9
10
11
XC3030A XC3020A
10
11
12
13
14
—
15
16
—
17
18
19
—
20
—
21
22
23
24
25
26
27
28
29
30
—
—
31
32
33
34
35
36
37
38
39
—
—
40
41
42
43
XC3030A XC3020A
44
45
46
47
48
—
49
50
51
—
52
53
54
55
—
—
56
57
58
59
60
61
62
63
64
—
—
65
66
67
68
1
2
3
4
5
—
—
6
7
8
9
10
11
—
12
13
—
14
15
16
17
18
19
—
20
21
22
—
23
24
25
26
27
28
29
30
31
44
45
46
47
48
—
49
50
51
—
52
53
54
55
—
—
56
57
58
59
60
61
62
63
64
—
—
65
66
67
68
1
2
3
4
5
—
—
6
7
8
9
32
33
—
34
35
36
37
38
39
40
41
42
43
相關(guān)PDF資料
PDF描述
XC3064L-8TQ144I Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3030A-6PC44C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3030A-6PC68C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
XC3030A-6PC84C Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3064L-8TQ144I 功能描述:IC FPGA 3.3V I-TEMP 144-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:XC3000A/L 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC3090 制造商:XILINX 制造商全稱:XILINX 功能描述:Logic Cell Array Families
XC3090-100CB164B 制造商:Xilinx 功能描述:
XC3090-100CB164C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
XC3090-100CB164M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA)
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