參數(shù)資料
型號: XC3030A-7PC68I
廠商: XILINX INC
元件分類: FPGA
英文描述: Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述: FPGA, 100 CLBS, 1500 GATES, 113 MHz, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 30/76頁
文件大小: 731K
代理商: XC3030A-7PC68I
R
XC3000 Series Field Programmable Gate Arrays
7-32
November 9, 1998 (Version 3.1)
Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the FPGA.
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. At power-up, V
must rise from 2.0 V to V
min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long V
CC
rise time of >100 ms, or a
non-monotonically rising V
may require a >6-
μ
s High level on RESET, followed by a >6-
μ
s Low level on RESET and D/P
after V
CC
has reached 4.0 V (2.5 V for the XC3000L).
Figure 30: Slave Serial Mode Programming Switching Characteristics
4 T
CCH
Bit n
Bit n + 1
Bit n
Bit n - 1
3 T
CCO
5 T
CCL
2 T
CCD
1 T
DCC
DIN
CCLK
DOUT
(Output)
X5379
Description
To DOUT
Symbol
T
CCO
Min
Max
100
Units
ns
CCLK
DIN setup
DIN hold
High time
Low time (Note 1)
Frequency
3
1
2
4
5
T
DCC
T
CCD
T
CCH
T
CCL
F
CC
60
0
0.05
0.05
5.0
10
ns
ns
μ
s
μ
s
MHz
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