參數(shù)資料
型號(hào)： XC3030A-7PC68C
廠商： XILINX INC
元件分類： FPGA
英文描述： Field Programmable Gate Arrays (XC3000A/L, XC3100A/L)
中文描述： FPGA, 100 CLBS, 1500 GATES, 113 MHz, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 57/76頁(yè)
文件大?。?/td> 731K
代理商： XC3030A-7PC68C
R
November 9, 1998 (Version 3.1)
7-59
XC3000 Series Field Programmable Gate Arrays
7
XC3100L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.
XC3100L Operating Conditions
Notes:
1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per
°
C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 V to 5.25 V, Xilinx reserves the right
to restrict operation to the 3.0 and 3.6 V range later, when smaller device geometries might preclude operation @ 5 V.
Operating conditions are guaranteed in the 3.0 – 3.6 V V
CC
range.
XC3100L DC Characteristics Over Operating Conditions
Notes:
1. With no output current loads, no active input or long line pull-up resistors, all package pins at V
CC
or GND, and the FPGA
configured with a tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source current may not
exceed 100 mA per V
CC
pin. The number of ground pins varies from the XC3142L to the XC3190L.
3. Not tested. Allows undriven pins to float High. For any other purpose, use an external pull-up.
Symbol
V
CC
V
IH
V
IL
T
IN
Description
Min
3.0
2.0
-0.3
Max
3.6
Units
V
V
V
ns
Supply voltage relative to GND Commercial 0
°
C to +85
°
C junction
High-level input voltage
Low-level input voltage
Input signal transition time
V
CC
+ 0.3
0.8
250
Symbol
Description
Min
2.4
Max
Units
V
V
V
V
V
mA
V
OH
High-level output voltage (@ I
OH
= -4.0 mA, V
CC
min)
High-level output voltage (@ I
OH
= -100.0
μ
A, V
CC
min)
Low-level output voltage (@ I
OH
= 4.0 mA, V
CC
min)
Low-level output voltage (@ I
OH
= +100.0
μ
A, V
CC
min)
Power-down supply voltage (PWRDWN must be Low)
Quiescent FPGA supply current
Chip thresholds programmed as CMOS levels
1
Input Leakage Current
Input capacitance
(sample tested)
All pins except XTL1 and XTL2
XTL1 and XTL2
Pad pull-up (when selected) @ V
IN
= 0 V
3
Horizontal long line pull-up (when selected) @ logic Low
V
CC
-0.2
V
OL
0.40
0.2
V
CCPD
I
CCO
2.30
1.5
I
IL
-10
+10
μ
A
C
IN
10
15
0.17
2.80
pF
pF
mA
mA
I
RIN
I
RLL
0.02
0.20
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