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| 型號(hào)： | XC3030A-7PC68C |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) |
| 中文描述： | FPGA, 100 CLBS, 1500 GATES, 113 MHz, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 26/76頁 |
| 文件大?。?/td> | 731K |
| 代理商： | XC3030A-7PC68C |
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R
XC3000 Series Field Programmable Gate Arrays
7-28
November 9, 1998 (Version 3.1)
Notes:
1. At power-up, V
must rise from 2.0 V to V
min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long V
CC
rise time of >100 ms, or a
non-monotonically rising V
CC
may require a >6-
μ
s High level on RESET, followed by a >6-
μ
s Low level on RESET and D/P
after V
has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
Figure 26: Master Parallel Mode Programming Switching Characteristics
Address for Byte n
Byte
2 T
DRC
Address for Byte n + 1
D7
D6
A0-A15
(output)
D0-D7
RCLK
(output)
CCLK
(output)
DOUT
(output)
1 T
RAC
7 CCLKs
CCLK
3 T
RCD
Byte n - 1
X5380
Description
Symbol
Min
0
60
0
600
4.0
Max
200
Units
ns
ns
ns
ns
μ
s
RCLK
To address valid
To data setup
To data hold
RCLK High
RCLK Low
1
2
3
T
RAC
T
DRC
T
RCD
T
RCH
T
RCL
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| XC3030A-7PC68C0090 | 制造商:Xilinx 功能描述: |
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