參數(shù)資料
型號: XC2S50E-6TQG144C
廠商: Xilinx Inc
文件頁數(shù): 11/108頁
文件大?。?/td> 0K
描述: IC SPARTAN-IIE FPGA 50K 144-TQFP
產(chǎn)品變化通告: FPGA Family Discontinuation 18/Apr/2011
標準包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 384
邏輯元件/單元數(shù): 1728
RAM 位總計: 32768
輸入/輸出數(shù): 102
門數(shù): 50000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
其它名稱: 122-1331
108
DS077-4 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Revision History
Date
Version
Description
11/15/2001
1.0
Initial Xilinx release.
12/20/2001
1.1
Corrected differential pin pair designations.
11/18/2002
2.0
Added XC2S400E and XC2S600E and FG676. Removed L37 designation from FT256 pinouts.
Minor corrections and clarifications to pinout definitions. Removed Preliminary designation.
02/14/2003
2.1
Added differential pairs table on page 57, fixed 3 P/N designation typos introduced in v2.0.
Clarified that XC2S50E has two VREF pins per bank.
06/18/2008
2.3
Added Package Overview section. Updated all modules for continuous page, figure, and table
numbering. Updated links. Synchronized all modules to v2.3.
08/09/2013
3.0
This product is obsolete/discontinued per XCN12026.
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