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參數(shù)資料
| 型號： | XC2S300E-8 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 115K |
| 代理商： | XC2S300E-8 |
May 20, 2002
1
0HPHF
&RUH
TM
Product Line
9980 Huennekens Street
San Diego, CA 92121
Americas:+1 888-360-9044
Europe:
+1 41 (0) 32 374 32 00
Asia:
+(852) 2410 2720
E-mail:
sales@memecdesign.com
URL:
www.memedesign.com
Features
Available under terms of the SignOnce IP License
Complies with USB protocol revision 1.1
Supports VCI to the application bus
Supports full-speed (12 Mbps) signaling bit rate
Supports low-speed (1.5 Mbps) signaling bit rate
Handles USB protocol
Handles USB device states
Clock and data recovery from USB
Microprocessor independent
Includes Suspend/Resume logic
Performs cyclic redundancy checks (CRC) with CRC5
checking, and CRC16 generation and checking
Supports up to fifteen configurations, with each
configuration supporting fifteen interfaces and each
interface handling up to fifteen alternate settings
Enables physical endpoint number programming and
supports up to 16 bidirectional logical endpoints
Table 1: Core Implementation Data
1
Features (contd)
Maintains data toggle bits
Enables user-configured endpoint information
Provides understanding and decoding of standard USB
commands to endpoint zero
Provides the option to decode the Get Descriptor
command or to pass the command to the application for
decoding
Supports class/vendor commands by passing the Setup
transactions to the application
Supports up to 15 string descriptors
Powered by
AllianceCORE Facts
Core Specifics
See Table 1
Provided with Core
Documentation
User manual, Implementation
guide, data sheet
Design File Formats
Verification
Constraints File
Instantiation Templates
Reference designs &
application notes
Additional Items
NGO netlist
Simulation model
.ucf
VHDL, Verilog
None
Warranty by MemecCore
Design Tool Requirements
Synthesis Tool
Simulation
Synplify Pro 6.0
ModelSim 5.4e
Support
Core support provided by MemecCore
Additional customization provided by Memec Design
Supported
Family
Virtex
-II
Spartan
-II
Virtex
-E
Notes:
1. These numbers reached with the following options, with the sample design: hard-coded registers, application and UDC using same
clock, the core does not decode get_descriptor, 1 interface, 1 alternate, 1 additional endpoint (bulk out), endpoint 0 maxpktsize is 8
bytes, endpoint 1 maxpktsize is 8 bytes
2. Assuming all core signals are routed off-chip.
3. Minimum guaranteed speed.
Device Tested
CLB
Slices
1036
1029
1029
Clock
IOBs
2
2
2
2
IOBs
2
Performance
(MHz)
3
12
12
12
Xilinx Tools
Special
Features
None
None
None
XC2V1000-5
XC2S200-5
XCV300E-8
117
117
117
Alliance 3.3iSP8
Alliance 3.3iSP8
Alliance 3.3iSP8
MC-XIL-USB11DEV
USB 1.1 Device Controller
May 20, 2002
Product Specification
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