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參數(shù)資料
| 型號(hào)： | XC2S200-5 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大小： | 115K |
| 代理商： | XC2S200-5 |
May 20, 2002
5
Memec Design
app_ack
In
The application asserts this signal to indicate the completion of data
transfer.
The application asserts this error signal during a data write, either to
stop the current burst transfer without transferring data, or to indicate to
the core that the application cannot complete the current transfer at this
time, and the core should retry the transaction at a later time.
The application asserts this signal to indicate that it is aborting the cur-
rent packet.
This is the data bus for read transactions.
This is the byte enable control for app_data[31:0].
app_err
In
app_abort
In
app_data[31:0]
app_databen[3:0]
Control/Status Register Interface Signals
app_csrcmdvalid
In
In
In
This signal is asserted by the application to access the Control/Status
Register (CSR) of the core.
This indicates the address of the register transaction is a read or write
transaction.
This indicates whether the current transaction is a read or write opera-
tion.
This indicates a burst transaction; the application should never assert
this signal.
This indicates which bytes are valid on the 32-bit app_crsdata bus.
This is the write data to be written to the addressed register during the
current transaction.
The core asserts this signal to acknowledge a successful data transfer
to the CSR.
This error indicates the start of a frame (SOF).
This signal should never be asserted by the core for CSR transactions.
It is tied to zero in the core.
The core provides this read data for CSR transactions.
app_csraddr[15:0]
In
app_csrrnw
In
app_csrburst
In
app_csrben[3:0]
app_csrdata[31:0]
In
In
udcvci_csrack
Out
udcvci_csrerr
udcvci_csrabort
Out
Out
udcvci_csrdata[31:0]
EEPROM Interface Signals
udcvci_eepsk
udcvci_eepcs
udcvci_eepdi
eep_do
Event Notification Signals
udcvci_suspend
udcvci_usbreset
udcvci_sof
ucvci_timestamp[10:0]
Debugging Signals
udcvci_cfg[3:0]
Out
Out
Out
Out
In
The core generates the low-speed clock signal to activate the EEPROM.
The core generates this chip select signal to enable the EEPROM.
This is the data signal input to the EEPROM.
This is the data signal input to the core.
Out
Out
Out
Out
This is the Suspend indication from the UDCVCI core to the application.
This is the Reset indication from the UDCVCI core to the application.
This signal indicates the start of a frame (SOF).
This indicates the SOF frame number.
Out
The signal indicates the current configuration the UDCVCI core is run-
ning.
This indicates the current interface that is switched to a different alter-
nate value.
This it the current alternate value for the interface.
This is the qualifying signal for sampling udcvcu_cfg[3:0].
This the qualifying signal for sampling udcvci_intf[3:0] and
ucvci_altinf[3:0].
udcvci_intf[3:0]
Out
udcvci_altintf[3:0]
udcvci_hst_setcfg
udcvci_hst_setintf
Out
Out
Out
Table 2: Core Signal Pinout (cont.)
Signal Name
Direction
Description
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PDF描述 |
|---|---|
| XC2S300E-8 | Telecomm/Datacomm |
| XC2S400E-6FG456C | FPGA |
| XC2S400E-6FG456I | FPGA |
| XC2S400E-6FG676C | FPGA |
| XC2S400E-6FG676I | FPGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S200-5CS144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S200-5CS144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S200-5CSG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S200-5CSG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-II FPGA Family |
| XC2S2005FG256C | 制造商:Xilinx 功能描述: |
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