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參數(shù)資料
| 型號(hào)： | XC2S100E-6TQ144C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 47/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V 600 CLB'S 144-TQFP |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | Spartan®-IIE |
| LAB/CLB數(shù)： | 600 |
| 邏輯元件/單元數(shù)： | 2700 |
| RAM 位總計(jì)： | 40960 |
| 輸入/輸出數(shù)： | 102 |
| 門數(shù)： | 100000 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 其它名稱： | 122-1206 |
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DS077-3 (v3.0) August 9, 2013
43
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
DLL Timing Parameters
Because of the difficulty in directly measuring many internal
timing parameters, those parameters are derived from
benchmark timing patterns. The following guidelines reflect
worst-case values across the recommended operating con-
ditions.
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were deter-
mined through statistical measurement at the package pins
using a clock mirror configuration and matched drivers.
Figure 22, page 44, provides definitions for various parame-
ters in the table below.
Symbol
Description
FCLKIN
Speed Grade
Units
-7
-6
Min
Max
Min
Max
FCLKINHF
Input clock frequency (CLKDLLHF)
-
60
320
60
275
MHz
FCLKINLF
Input clock frequency (CLKDLL)
-
25
160
25
135
MHz
TDLLPW
Input clock pulse width
≥25 MHz
5.0
-
5.0
-
ns
≥50 MHz
3.0
-
3.0
-
ns
≥100 MHz
2.4
-
2.4
-
ns
≥150 MHz
2.0
-
2.0
-
ns
≥200 MHz
1.8
-
1.8
-
ns
≥250 MHz
1.5
-
1.5
-
ns
≥300 MHz
1.3
-
NA
-
Symbol
Description
FCLKIN
CLKDLLHF
CLKDLL
Units
Min
Max
Min
Max
TIPTOL
Input clock period tolerance
-
1.0
-
1.0
ns
TIJITCC
Input clock jitter tolerance (cycle-to-cycle)
-
±150
-
±300
ps
TLOCK
Time required for DLL to acquire lock(1)
> 60 MHz
-
20
-
20
μs
50-60 MHz
-
25
μs
40-50 MHz
-
50
μs
30-40 MHz
-
90
μs
25-30 MHz
-
120
μs
TOJITCC
Output jitter (cycle-to-cycle) for any DLL clock output(2)
-
±60
-
±60
ps
TPHIO
Phase offset between CLKIN and CLKO(3)
-
±100
-
±100
ps
TPHOO
Phase offset between clock outputs on the DLL(4)
-
±140
-
±140
ps
TPHIOM
Phase difference between CLKIN and CLKO(5)
-
±160
-
±160
ps
TPHOOM
Phase difference between clock outputs on the DLL(6)
-
±200
-
±200
ps
Notes:
1.
Commercial operating conditions. Add 30% for Industrial operating conditions.
2.
Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
3.
Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
4.
Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding output jitter and input clock jitter.
5.
Maximum Phase Difference between CLKIN and CLKO is the sum of output jitter and phase offset between CLKIN and CLKO, or
the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
6.
Maximum Phase Difference between Clock Outputs on the DLL is the sum of output jitter and phase offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XC2S100E-6TQ144C0776 | 制造商:Xilinx 功能描述: |
| XC2S100E-6TQ144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE 1.8V FPGA Family |
| XC2S100E-6TQG144C | 功能描述:IC FPGA 1.8V 600 CLB'S 144-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:Spartan®-IIE 標(biāo)準(zhǔn)包裝:40 系列:Spartan® 6 LX LAB/CLB數(shù):3411 邏輯元件/單元數(shù):43661 RAM 位總計(jì):2138112 輸入/輸出數(shù):358 門數(shù):- 電源電壓:1.14 V ~ 1.26 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:676-BGA 供應(yīng)商設(shè)備封裝:676-FBGA（27x27） |
| XC2S100E-6TQG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S100E7FG456C | 制造商:Xilinx 功能描述: |
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