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參數(shù)資料
| 型號： | X9268UV24 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/22頁 |
| 文件大小： | 0K |
| 描述： | IC XDCP DUAL 256TAP 50K 24-TSSOP |
| 標準包裝： | 62 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 2 |
| 溫度系數(shù)： | 標準值 ±300 ppm/°C |
| 存儲器類型： | 非易失 |
| 接口： | I²C（設備位址） |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 24-TSSOP |
| 包裝： | 管件 |
16
FN8172.4
August 29, 2006
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
POWER-UP AND DOWN REQUIREMENTS
The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The VCC ramp rate spec is always in effect.
A.C. TEST CONDITIONS
Notes: (6) This parameter is not 100% tested
(7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued.
These parameters are periodically sampled and not 100% tested.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
ICC1
VCC supply current
(active)
fSCL = 400kHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active, Read and
Volatile Write States only)
3mA
ICC2
VCC supply current
(nonvolatile write)
fSCL = 400kHz; VCC = +6V;
SDA = Open; (for 2-Wire, Active,
Nonvolatile Write State only)
5mA
ISB
VCC current (standby)
VCC = +6V; VIN = VSS or VCC;
SDA = VCC; (for 2-Wire, Standby State only)
5
A
ILI
Input leakage current
VIN = VSS to VCC
10
A
ILO
Output leakage current
VOUT = VSS to VCC
10
A
VIH
Input HIGH voltage
VCC x 0.7
VCC + 1
V
VIL
Input LOW voltage
-1
VCC x 0.3
V
VOL
Output LOW voltage
IOL = 3mA
0.4
V
VOH
Output HIGH voltage
Parameter
Min.
Units
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
years
Symbol
Test
Max.
Units
Test Conditions
CIN/OUT(6)
Input / Output capacitance (SDA)
8
pF
VOUT = 0V
CIN(6)
Input capacitance (SCL, WP, A3, A2, A1 and A0)6
pF
VIN = 0V
Symbol
Parameter
Min.
Max.
Units
tr VCC(6)
VCC Power-up rate
0.2
50
V/ms
tPUR(7)
Power-up to initiation of read operation
1
ms
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
X9268
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