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參數(shù)資料
| 型號： | X88C75P |
| 英文描述： | Port Expander and E2 Memory |
| 中文描述： | 端口擴展和E2內(nèi)存 |
| 文件頁數(shù)： | 2/27頁 |
| 文件大?。?/td> | 125K |
| 代理商： | X88C75P |
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X88C75 SLIC
E
2
2
Reading and writing of the nonvolatile memory array is
analogous to RAM operation. During a write operation to
either the nonvolatile memory or the control registers,
ALE latches the address to be written into the X88C75.
The rising edge of
WR
latches the data to be written.
The nonvolatile memory of the X88C75 is internally
organized as two independent arrays of 4K-bytes with
the A12 input selecting which of the two planes of
memory is to be accessed. While the processor is
executing code out of one plane, write operations can
take place in the other plane; allowing the processor to
continue execution of code out of the X88C75 during a
byte or page write to the device. This feature is called
Concurrent Read During Write.
The X88C75 also features an advanced implementation
of the Software Data Protection scheme, called Block
Lock Protect, which allows the nonvolatile memory array
to be treated as 8 independent sections of 1K-bytes.
Each of these sections can be independently enabled
for write operations. This allows segmentation of the
memory contents into writable and non-writable sec-
tions, thereby, allowing certain sections of the device to
be secured so that updates can only occur in a controlled
environment. (e.g. in an automotive application, only at
which allows Individual blocks of the memory to be
configured as read-only or read/write.
Each bidirectional port consists of 8 general purpose
I/O lines and 1 data strobe line. The ports also feature a
configurable interrupt request output.
Access to the X88C75 is accomplished through the
multiplexed address/data bus of the 80C51 type control-
lers. An internal programmable address decoder maps
the internal memory and register locations into the
desired address space.
ARCHITECTURAL OVERVIEW
The X88C75 incorporates the interface circuitry nor-
mally needed to decode the control signals and
demultiplex the address/data bus to provide a “seam-
less” interface.
The control inputs on the X88C75 are configured such
that it is possible to directly connect them to the proper
interface signals of the 80C51 microcontroller. The
reading of data from the chip is controlled either by the
PSEN
or the
RD
signal, which essentially maps the
X88C75 into both the Program and the Data Memory
address map.
FUNCTIONAL DIAGRAM
2887 ILL F03
ADDRESS
LATCH
I/O
BUFFER
&
LATCH
MASTER
CONTROL
LOGIC
LEFT PLANE
DECODE
RIGHT PLANE
DECODE
1K X 8
1K X 8
E2PROM
CE
ALE
PSEN
RD
WR
RESET
IRQ
1K X 8
1K X 8
1K X 8
1K X 8
E2PROM
1K X 8
1K X 8
SDP
DECODE
CONFIG
REGISTER
MAP
MEM.
PORT
SPECIAL
FUNCTION
REGISTERS
PORT
A
PORT
B
PORT SELECT
DATA I/O BUS
A0–A15
I/O0–I/O7
WC
16 X 8
GENERAL
PURPOSE
REGISTERS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X88C75PI | Port Expander and E2 Memory |
| X88C75PM | Port Expander and E2 Memory |
| X9102P | Digital Potentiometer |
| X9102PI | Digital Potentiometer |
| X9102S | Digital Potentiometer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X88C75PI | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Port Expander and E2 Memory |
| X88C75PM | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Port Expander and E2 Memory |
| X8934 | 功能描述:固態(tài)繼電器-工業(yè)安裝 0381 SLD. R RELAY RoHS:否 制造商:Crydom 控制電壓范圍:4 VDC to 32 VDC 負(fù)載電壓額定值:7 VDC to 72 VDC 負(fù)載電流額定值:160 A 觸點形式: 輸出設(shè)備:SSR 安裝風(fēng)格:Panel |
| X8989-34 | 制造商:Cooper Crouse-Hinds 功能描述: 制造商:CROUSE-HINDS/COOPER 功能描述: |
| X89C205VGEAF | 制造商:USMC 功能描述: |
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