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參數(shù)資料
| 型號： | X79002V20IT1 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/18頁 |
| 文件大小： | 0K |
| 描述： | IC DAC NV SELECT OUT/MEM 20TSSOP |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | 417k |
11
FN8147.0
March 17, 2005
FUNCTIONAL DESCRIPTION
DAC Register Clear Function
When the input pin CLR is set to logic high, the DAC
volatile register and serial input registers are reset to 000
hex. CLR is an asynchronous input. CLR has an on-chip
pulldown. CLR is ignored while RDY is high.
Buffer Output Enable Function
When the input pin OE is set to logic low, the DAC
buffered output, Vbuf, is set to high impedance.
When the input pin OE is at a logic high, the DAC
buffered output is enabled.
UP/DOWN Interface
The UP/DOWN Interface can be used to change the
value of the DAC register without using the serial
Interface.
The CS pin must be HIGH, when the UP/DOWN
Interface is used, to set the serial interface in standby
mode.
Control bits Count8 and Count10 determine the binary
word that is incremented or decremented, according to
the following table:
These control bits are set by performing a Write
Operation with the serial interface prior to operation of
the UP/DOWN interface.
For example, when Count8 is one, the DAC register
is affected by increment or decrement operations as
follows:
A HIGH to LOW transition on the UP pin, while the
DOWN pin is LOW, increments the selected binary word
by one.
A HIGH to LOW transition on the DOWN pin, while
the UP pin is LOW, decrements the selected binary
word by one.
Other combinations are not valid. See the following table
for a summary of these operations.
X = Don’t Care
RDY Pin
The RDY pin is an open drain output which will follow the
VCC voltage on power-up (due to the pullups) resistor
and will transition to a low state at time tRDY after VCC
reaches a minimum voltage (VRDY). As long as VCC is
higher the VRDY, the output will remain low. If VCC falls
below VRDY, the RDY output will return to a high state.
Count8
Count10
Part of DAC register
incremented or
decremented.
0
The complete 12 bit word is used
0
1
10 MSBs are used
1
0
8 MSBs are used
11
Reserved
8 MSBs
4 LSBs
1000 1011
1000 1010
1110
Increment
1000 1001
1110
Initial Value
1000 1000
1000 0111
1110
Decrement
CS
Up
Down
Mode
L
X
SPI Control
H
L
Increment
H
L
Decrement
H
Not Allowed
H
Not Allowed
X79000, X79001, X79002
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