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參數(shù)資料
| 型號(hào)： | X79002V20IT1 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 15/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC NV SELECT OUT/MEM 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | 417k |
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6
FN8147.0
March 17, 2005
Notes: 1. INL, DNL, Offset Error and Full Scale error measured at Vbuf with VFB connected to Vbuf.
2. The VL and VH levels are set using the configuration register according to the following table:
This setting corresponds to the nominal values of VH = 3.025V and VL = 0.151V
3. INL is measured at the maximum range of (VH-VL). INL varies inversely with the range of (VH-VL). DNL increases at lower
(VH-VL) ranges but the DAC retains montonicity.
4. Total offset error scales with VL according to (1% x VL) + 10mV and total full scale error scales with VH according to (1% x VH) + 10mV
5. Guaranteed by characterization, not 100% tested.
6. fSCK = 5MHz, using SPI interface test conditions on pg. 8.
ENDURANCE AND DATA RETENTION (VCC = 5V ±10%, TA = Full Operating Temprature Range)
SYMBOL TABLE
VPOR
Power-on reset threshold voltage
1.5
2.8
V
VRDY
RDY indicator minimum voltage
2.6
2.8
V
See figure 1.
TRDY
RDY indicator delay
100
6000
s
2k
and 100pF between Vcc and
RDY (4)
Address
VH2
VH1
VH0
VL2
VL1
VL0
Count 8
Count 10
3Ch
1
0
1
0
1
X
X = don’t care
Parameter
Minimum endurance
100,000
Data changes per bit
Data retention
10
Years
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions / Notes
FIGURE 1. RDY PIN TIMING
VRDY
V(RDY)
0V
TRDY
Device
Ready
Power-down
Device Disabled
VCC
Time
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
VOUT
OE
tOEDIS
tOEVALID
Vbuf = High Impedance
Vbuf OUTPUT ENABLE TIMING
X79000, X79001, X79002
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