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參數(shù)資料
| 型號： | WV3HG128M72AER403AD6EG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封裝： | ROHS COMPLIANT, DIMM-240 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 157K |
| 代理商： | WV3HG128M72AER403AD6EG |
WV3HG128M72AER-AD6
ADVANCED
9
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
October 2006
Rev. 2
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNIT
Command
and
Address
Address and control input pulse width for each input
tIPW
0.6
tCK
Address and control input setup time
tIS
250
350
ps
Address and control input hold time
tIH
375
475
ps
CAS# to CAS# command delay
tCCD
22
tCK
ACTIVE to ACTIVE (same bank) command
tRC
60
55
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
15
ns
Four Bank Activate period
tFAW
37.5
ns
ACTIVE to PRECHARGE command
tRAS
45
70,000
40
70,000
ns
Internal READ to precharge command delay
tRTP
7.5
ns
6 Write recovery time
tWR
15
ns
Auto precharge write recovery + precharge time
tDAL
tWR + tRP
ns
Internal WRITE to READ command delay
tWTR
7.5
10
ns
PRECHARGE command period
tRP
15
ns
PRECHARGE ALL command period
tRPA
tRP+tCK
ns
LOAD MODE command cycle time
tMRD
22
tCK
OCD Drive mode delay
tOIT
012012
ns
CKE low to CK,CK# uncertainty
tDELAY
tIS + tCK + tIH
ns
Refresh
REFRESH to REFRESH command interval
tRFC
105
70,000
105
70,000
ns
Average periodic refresh interval
tREFI
7.8
s
Self
Refresh
Exit self refresh to non-READ command
tXSNR
tRFC (MIN) + 10
ns
Exit self refresh to READ command
tXSRD
200
tCK
Exit self refresh timing reference
tISXR
tIS
ps
Exit self refresh timing reference
tISXR
250
350
ps
ODT
ODT turn-on delay
tAOND
2222
tCK
ODT turn-on
tAON
tAC (MIN)
tAC (MAX) +
1000
tAC (MIN)
tAC (MAX) +
1000
ps
ODT turn-off delay
tAOFD
2.5
tCK
ODT turn-off
tAOF
tAC (MIN)
tAC (MAX) +
600
tAC (MIN)
tAC (MAX) +
600
ps
ODT turn-on (power-down mode)
tAONPD
tAC (MIN) +
2000
2 x tCK +
tAC (MAX) +
1000
tAC (MIN) +
2000
2 x tCK +
tAC (MAX) +
1000
ps
ODT turn-off (power-down mode)
tAOFPD
tAC (MIN) +
2000
2.5 x tCK +
tAC (MAX) +
1000
tAC (MIN) +
2000
2.5 x tCK +
tAC (MAX) +
1000
ps
ODT to power-down entry latency
tANPD
33
tCK
ODT power-down exit latency
tAXPD
88
tCK
Power-Down
Exit active power-down to READ command, MR[bit12=0]
tXARD
22
tCK
Exit active power-down to READ command, MR[bit12=1]
tXARDS
6 - AL
tCK
A Exit precharge power-down to any non-READ command.
tXP
22
tCK
CKE minimum high/low time
tCKE
33
tCK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WV3HG128M72AER403AD6IEG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR2 SDRAM RDIMM, VLP |
| WV3HG128M72AER403AD6IMG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR2 SDRAM RDIMM, VLP |
| WV3HG128M72AER403AD6ISG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR2 SDRAM RDIMM, VLP |
| WV3HG128M72AER403AD6MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR2 SDRAM RDIMM, VLP |
| WV3HG128M72AER403AD6SG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx72 DDR2 SDRAM RDIMM, VLP |
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