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參數(shù)資料
| 型號： | WEDPN4M64V-125BM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 64 SYNCHRONOUS DRAM, 6 ns, PBGA219 |
| 封裝： | 21 X 21 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 385K |
| 代理商： | WEDPN4M64V-125BM |
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specications without notice.
TABLE 1 – BURST DEFINITION
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
2
A0
0
0-1
1
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
n = A0-9/8/7
(location 0-y)
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
Not Supported
FIGURE 2 – MODE REGISTER DEFINITION
M3 = 0
1
2
4
8
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7 A6
A5 A4
A3
A8
A2
A1 A0
Mode Register (Mx)
Address Bus
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Op Mode
A10
A11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
NOTES:
1.
For full-page accesses: y = 256.
2.
For a burst length of two, A1-7 select the block-of-two burst; A0 selects the starting
column within the block.
3.
For a burst length of four, A2-7 select the block-of-four burst; A0-1 select the starting
column within the block.
4.
For a burst length of eight, A3-7 select the block-of-eight burst; A0-2 select the
starting column within the block.
5.
For a full-page burst, the full row is selected and A0-7 select the starting column.
6.
Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7.
For a burst length of one, A0-7 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
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