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參數(shù)資料
| 型號(hào)： | WEDPN4M64V-125BM |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 4M X 64 SYNCHRONOUS DRAM, 6 ns, PBGA219 |
| 封裝： | 21 X 21 MM, PLASTIC, BGA-219 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 385K |
| 代理商： | WEDPN4M64V-125BM |
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPN4M64V-XBX
January 2005
Rev. 8
White Electronic Designs Corp. reserves the right to change products or specications without notice.
TRUTH TABLE – COMMANDS AND DQM OPERATION (NOTE 1)
Name (Function)
CS#
RAS#
CAS#
WE#
DQM
ADDR
I/Os
COMMAND INHIBIT (NOP)
H
X
NO OPERATION (NOP)
L
H
X
ACTIVE (Select bank and activate row) ( 3)
L
H
X
Bank/Row
X
READ (Select bank and column, and start READ burst) (4)
L
H
L
H
L/H8
Bank/Col
X
WRITE (Select bank and column, and start WRITE burst) (4)
L
H
L
L/H8
Bank/Col
Valid
BURST TERMINATE
L
H
L
X
Active
PRECHARGE (Deactivate row in bank or banks) ( 5)
L
H
L
X
Code
X
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
L
H
X
LOAD MODE REGISTER (2)
L
X
Op-Code
X
Write Enable/Output Enable (8)
––––
L
–
Active
Write Inhibit/Output High-Z (8)
––––
H
–
High-Z
NOTES:
1.
CKE is HIGH for all commands shown except SELF REFRESH.
2.
A0-11 dene the op-code written to the Mode Register.
3.
A0-11 provide row address, and BA0, BA1 determine which bank is made active.
4.
A0-7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is
being read from or written to.
5.
A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6.
This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8.
Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs (two-clock delay).
on inputs A0-11 selects the row. This row remains active
(or open) for accesses until a PRECHARGE command is
issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-7
selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ burst;
if AUTO PRECHARGE is not selected, the row will remain
open for subsequent accesses. Read data appears on
the I/Os subject to the logic level on the DQM inputs two
clocks earlier. If a given DQM signal was registered HIGH,
the corresponding I/Os will be High-Z two clocks later; if
the DQM signal was registered LOW, the I/Os will provide
valid data.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-7
COMMAND INHIBIT
The COMMAND INHIBIT function prevents new commands
from being executed by the SDRAM, regardless of whether
the CK signal is enabled. The SDRAM is effectively
deselected. Operations already in progress are not
affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform
a NOP to an SDRAM which is selected (CS# is LOW).
This prevents unwanted commands from being registered
during idle or wait states. Operations already in progress
are not affected.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-11. See Mode
Register heading in the Register Denition section. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in
a particular bank for a subsequent access. The value on the
BA0, BA1 inputs selects the bank, and the address provided
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