參數(shù)資料
型號： WED2DG472512V65D2
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： SRAM
英文描述： 2M X 72 MULTI DEVICE SRAM MODULE, 3.7 ns, DMA168
封裝： DIMM-168
文件頁數(shù)： 5/10頁
文件大?。?/td> 181K
代理商： WED2DG472512V65D2
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WED2DG472512V-D2
January 2000
Rev. 0
ADVANCED
White Electronic Designs Corp. reserves the right to change products or specications without notice.
SYNCHRONOUS ONLY – TRUTH TABLE
SYNC BURST – TRUTH TABLE
Operation
E1#E2#E3#E4#
GW#
G#
ZZ
CK
DQ
Synchronous Write - Bank 1
L
H
L
H
L
High-Z
Synchronous Read - Bank 1
L
HHHH
L
Synchronous Write - Bank 2
H
L
H
L
H
L
High-Z
Synchronous Read - Bank 2
H
L
H
L
Synchronous Write - Bank 3
H
L
H
L
H
L
High-Z
Synchronous Read - Bank 3
H
L
H
L
Synchronous Write - Bank 4
H
L
H
L
High-Z
Synchronous Read - Bank 4
H
L
H
L
Snooze Mode
XXXXXX
H
X
High-Z
Operation
E1#
E2#
E3#
E4#
ADSP# ADSC# ADV#
GW#
G#
CK
DQ
Addr. Used
Deselected Cycle, Power Down; Bank 1
H
X
L
X
L-H
High-Z
None
Deselected Cycle, Power Down; Bank 2
X
H
X
L
X
L-H
High-Z
None
Read Cycle, Begin Burst; Bank 1
L
H
L
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H
L-H
High-Z
External
Read Cycle, Begin Burst, Bank 2
H
L
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
X
H
L-H
High-Z
External
Write Cycle, Begin Burst; Bank 1
L
H
L
X
L
X
L-H
D
External
Write Cycle, Begin Burst; Bank 2
H
L
H
L
X
L
X
L-H
D
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
L-H
High-Z
External
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 1
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L-H
High-Z
Next
Write Cycle, Continue Burst; Bank 1
X
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H
X
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
L
X
L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 1
H
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H
X
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L-H
High-Z
Current
Write Cycle, Suspend Burst; Bank 1
X
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H
X
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
L
X
L-H
D
Current
Note
A
Note A: All truth Table Functions Repeat for Bank 3 (E3#) and Bank 4 (E4#).
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