- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄300104 > WEDPN8M72VR-66I (WHITE ELECTRONIC DESIGNS CORP) 8M X 72 SYNCHRONOUS DRAM MODULE, 7.5 ns, PBGA219 PDF資料下載
參數(shù)資料
| 型號(hào)： | WEDPN8M72VR-66I |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 72 SYNCHRONOUS DRAM MODULE, 7.5 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大?。?/td> | 208K |
| 代理商： | WEDPN8M72VR-66I |
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
HI-RELIABILITY PRODUCT
WEDPN8M72VR-XBX
December 2000 Rev. 1
GENERAL DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dynamic
random-access ,memory using 5 chips containing 134,217,728
bits. Each chip is internally configured as a quad-bank DRAM with
a synchronous interface. Each of the chip’s 33,554,432-bit banks
is organized as 4,096 rows by 512 columns by 16 bits. The MCP
also incorporates two 16-bit universal bus drivers for address and
input control signals.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence. Ac-
cesses begin with the registration of an ACTIVE command, which
is then followed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are used to
select the bank and row to be accessed (BA0, BA1 select the bank;
A0-11 select the row). The address bits registered coincident with
the READ or WRITE command are used to select the starting
column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst lengths
of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option.
An AUTO PRECHARGE function may be enabled to provide a self-
timed row precharge that is initiated at the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture to achieve
high-speed operation. This architecture is compatible with the 2
n rule
of prefetch architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed, fully random
access. Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seamless, high-
speed, random-access operation.
The 512Mb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along with a
power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer substan-
tial advances in DRAM operating performance, including the ability to
synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between internal banks
in order to hide precharge time and the capability to randomly change
column addresses on each clock cycle during a burst access.
8Mx72 Registered Synchronous DRAM ADVANCED*
FEATURES
s Registered for enhanced performance of bus speeds of 66 MHz
and 100 MHz
s Package:
219 Plastic Ball Grid Array (PBGA), 32 x 25mm
s Single 3.3V
±0.3V power supply
s Fully Synchronous; all signals registered on positive edge of
system clock cycle
s Internal pipelined operation; column address can be changed
every clock cycle
s Internal banks for hiding row access/precharge
s Programmable Burst length 1,2,4,8 or full page
s 4096 refresh cycles
s Commercial, Industrial and Military Temperature Ranges
s Organized as 8M x 72
s Weight: WEDPN8M72VR-XBX - 2.5 grams typical
BENEFITS
s 48% SPACE SAVINGS
s Reduced part count
s Reduced I/O count
40% I/O Reduction
s Laminate interposer for optimum TCE match
s Glueless connection to memory controller/PCI bridge
s Suitable for hi-reliability applications
s Upgradeable to 16M x 72 density (contact factory for information)
* This data sheet describes a product under development, non-qualified, and is
subject to change without notice.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| WG1602B-Y-JCS | WP1602B-Y-JCS |
| WG160PRW40 | TWO PART BOARD CONNECTOR |
| WG2002A-Y-JCS | WP2002A-Y-JCS |
| WG92SAW24SY-1 | 92 CONTACT(S), FEMALE, STRAIGHT TWO PART BOARD CONNECTOR, WIRE WRAP, RECEPTACLE |
| WGA122PR7 | TWO PART BOARD CONNECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPN8M72VR-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Registered SDRAM MCP |
| WEDPN8M72V-XB2X | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM |
| WEDPN8M72V-XBX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM MCP |
| WEDPNF8M721V-1010BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M721V-1010BI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。