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參數資料
| 型號： | W3EG7232S265BD4-M |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | SO-DIMM-200 |
| 文件頁數： | 2/14頁 |
| 文件大?。?/td> | 308K |
| 代理商： | W3EG7232S265BD4-M |
10
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7232S-AD4
-BD4
August 2005
Rev. 4
PRELIMINARY
34. VIH overshoot: VIH(MAX) = VCCQ + 1.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a
pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
35. VCC and VCCQ must track each other.
36. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
37. tRPST end point and tRPRE begin point are not referenced to a specic voltage level
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
39. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are
0Vs, provided a minimum of 42 0 of series resistance is used between the VTT
supply and the input pin.
40. The current part operates below the slowest JEDEC operating frequency of 83
MHz. As such, future die may not reect this option.
41. Random addressing changing and 50 percent of data changing at every transfer.
42. Random addressing changing and 100 percent of data changing at every transfer.
43. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tREF later.
44. IDD2N species the DQ, DQS, and DM to be driven to a valid high or low logic level.
IDD2Q is similar to IDD2F except IDD2Q species the address and control inputs to
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
45. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset. This is followed by 200 clock cycles.
46. Leakage number reects the worst case leakage possible through the module pin,
not what each memory device contributes.
47. When an input signal is HIGH or LOW, it is dened as a steady state logic HIGH or
LOW.
48. The 335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) =
120,000ns at any slower frequency.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| W3EG7232S265BD4-X | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7232S335AD4-X | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7232S335BD4-X | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7232S-AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7232S-BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL |
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