- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄231494 > W3EG7232S265BD4-M (MICROSEMI CORP-PMG MICROELECTRONICS) 32M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 PDF資料下載
參數(shù)資料
| 型號(hào)： | W3EG7232S265BD4-M |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | SO-DIMM-200 |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大?。?/td> | 308K |
| 代理商： | W3EG7232S265BD4-M |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)當(dāng)前第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7232S-AD4
-BD4
August 2005
Rev. 4
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C
≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Parameter
Symbol Conditions
DDR333@
CL=2.5
DDR266@
CL=2, 2.5
DDR200@
CL=2
Units
Max
Operating Current
IDD0
One device bank; Active - Precharge; (MIN); DQ,DM and
DQS inputs changing once per clock cycle; Address and
control inputs changing once every two cycles. TRC=TRC(MIN);
TCK=TCK
1400
mA
Operating Current
IDD1
One device bank; Active-Read-Precharge; Burst = 2;
TRC=TRC(MIN);TCK=TCK (MIN); Iout = 0mA; Address and
control inputs changing once per clock cycle.
1805
1715
mA
Precharge Power-Down
Standby Current
IDD2P
All device banks idle; Power-down mode; TCK=TCK(MIN);
CKE=(low)
36
mA
Idle Standby Current
IDD2F
CS# = High; All device banks idle; TCK=TCK(MIN); CKE = high;
Address and other control inputs changing once per clock
cycle. VIN = VREF for DQ, DQS and DM.
725
680
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode; TCK(MIN);
CKE=(low)
270
225
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device bank; Active-Precharge;
TRC=TRAS(MAX); TCK=TCK(MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address and other control
inputs changing once per clock cycle.
815
725
mA
Operating Current
IDD4R
Burst = 2; Reads; Continous burst; One device bank
active;Address andcontrol inputs changing once per clock
cycle; TCK=TCK(MIN); IOUT = 0mA.
1850
1625
mA
Operating Current
IDD4W
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
TCK=TCK(MIN); DQ,DM and DQS inputs changing twice per
clock cycle.
1850
1625
mA
Auto Refresh Current
IDD5
TRC=TRC(MIN)
2570
2390
mA
Self Refresh Current
IDD6
CKE ≤ 0.2V
311
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto precharge with
TRC=TRC (MIN); TCK=TCK(MIN); Address and control inputs
change only during Active Read or Write commands
3965
3425
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W7NCF02GH10CSA9HM1G | FLASH 3.3V PROM MODULE, XMA50 |
| W7NCF02GH10IS5BM1G | FLASH 3.3V PROM MODULE, XMA50 |
| W7NCF02GH10IS7DM1G | FLASH 3.3V PROM MODULE, XMA50 |
| W7NCF02GH10ISA4EM1G | FLASH 3.3V PROM MODULE, XMA50 |
| W7NCF02GH10ISA8EM1G | FLASH 3.3V PROM MODULE, XMA50 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG7232S265BD4-X | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7232S335AD4-X | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7232S335BD4-X | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7232S-AD4 | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7232S-BD4 | 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM UNBUFFERED w/PLL |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。