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參數(shù)資料
| 型號(hào)： | W24B02B-70LI |
| 廠(chǎng)商： | WINBOND ELECTRONICS CORP |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 256K X 8 STANDARD SRAM, 70 ns, PBGA48 |
| 封裝： | TFBGA-48 |
| 文件頁(yè)數(shù)： | 9/11頁(yè) |
| 文件大?。?/td> | 194K |
| 代理商： | W24B02B-70LI |
Preliminary W24B02
Publication Release Date: May 6, 2002
- 7 -
Revision A1
Timing Waveforms, continued
Write Cycle 2
(#OE = VIL Fixed)
#WE
DOUT
DIN
TAS
TDH
TWP
TWHZ
DW
T
(2)
(3)
TOW
TOH
AW
T
(1, 4)
TCW
TWR
Address
T WC
#CS
Notes:
1. During this period, I/O pins are in the output state, so input signals of opposite phase to the outputs should not be applied.
2. The data output from DOUT are the same as the data written to DIN during the write cycle.
3. DOUT provides the read data for the next address.
4. Transition is measured
±500 mV from steady state with CL = 5 pF. This parameter is guaranteed but not 100% tested.
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