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參數(shù)資料
| 型號(hào)： | VT8501 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | APOLLO MVP4 |
| 中文描述： | 阿波羅MVP4 |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大?。?/td> | 243K |
| 代理商： | VT8501 |
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VT8501 Apollo MVP4
Revision 1.3
February 1, 2000
-
7-
System Overview
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Apollo MVP4 Core Logic Overview
The Apollo MVP4
–
System Media Accelerated North Bridge (SMA) is a high performance, cost-effective and energy efficient
solution for the implementation of Integrated 2D/3D Graphics - PCI - ISA personal computer systems from 66 MHz to 100 MHz
based on 64-bit Socket-7 (Intel Pentium and Pentium MMX; AMD K6 and K6-2; Cyrix / National 6x86 / 6x86MX, IDT / Centaur
C6/WinChip), and Rise MP6 processors.
The Apollo MVP4 controller provides superior performance between the integrated 2D/3D Graphics Engine, CPU, optional
synchronous cache, DRAM, and PCI bus with pipelined, burst, and concurrent operation. For L2-Cache solutions using pipelined
burst synchronous SRAMs, 3-1-1-1-1-1-1-1 timing can be achieved for both read and write transactions at 100 MHz. Tag timing
is specially optimized internally (less than 4 nsec setup time) to allow implementation of L2 cache using an external tag for the
most flexible cache organization (0K / 256K / 512K / 1M / 2M). Four cache lines (16 quadwords) of CPU/cache to DRAM write
buffers with concurrent write-back capability are included on chip to speed up cache read and write miss cycles.
The Apollo MVP4 supports six banks of DRAMs up to 768MB. The DRAM controller supports standard Fast Page Mode (FP)
DRAM, EDO-DRAM, Synchronous DRAM (SDRAM), and Virtual Channel Synchronous DRAM in a flexible mix / match
manner. The Synchronous DRAM interface allows zero wait state bursting between the DRAM and the data buffers at 100 MHz.
The six banks of DRAM can be composed of an arbitrary mixture of 1M / 2M / 4M / 8M / 16MxN DRAMs. The DRAM
controller also supports optional ECC (single-bit error correction and multi-bit detection) or EC (error checking) capability
separately selectable on a bank-by-bank basis. The DRAM Controller can run at either the host CPU bus frequency (66 / 100
MHz) or at the PC100 memory frequency (100 MHz) with built-in deskew PLL timing control. With the advanced DRAM
controller, the Apollo MVP4 allows implementation of the most flexible, reliable, and high-performance DRAM interface.
The Apollo MVP4 also supports full AGP v2.0 capability with the internal 2D/3D Graphics Engine for maximum software
compatibility. An eight level request queue plus a four level post-write request queue with thirty-two and sixteen quadwords of
read and write data FIFO
’
s respectively are included for deep pipelined and split AGP transactions. A single-level GART TLB
with 16 full associative entries and flexible CPU/AGP/PCI remapping control is also provided for operation under protected mode
operating environments. Both Windows-95 VXD and Windows-98 / NT5 miniport drivers are supported.
The Apollo MVP4 supports one 32-bit 3.3 / 5V system bus (PCI) that is synchronous / pseudo-synchronous to the CPU bus. The
chip also contains a built-in AGP bus -to- PCI bus bridge to allow simultaneous concurrent operations on each bus. Five levels
(doublewords) of posted write buffers are included to allow for concurrent CPU and PCI operation. For PCI master operation,
forty-eight levels (doublewords) of posted write buffers and sixteen levels (doublewords) of prefetch buffers are included for
concurrent PCI bus and DRAM/cache accesses. The chip also supports enhanced PCI bus commands such as Memory-Read-Line,
Memory-Read-Multiple, and Memory-Write-Invalid commands to minimize snoop overhead. In addition, advanced features are
supported such as snoop ahead, snoop filtering, L1 write-back forward to PCI master, and L1 write-back merged with PCI post
write buffers to minimize PCI master read latency and DRAM utilization. Delayed transaction and read caching mechanisms are
also implemented for further improvement of overall system performance.
The Apollo MVP4 provides independent clock stop control for the CPU / SDRAM, PCI, and AGP buses and Dynamic CKE
control for powering down of the SDRAM. A separate suspend-well plane is implemented for the SDRAM control signals for
Suspend-to-DRAM operation. Coupled with the 324-pin Ball Grid Array VIA VT82C596B south bridge chip, a complete PC
main board can be implemented with no external TTLs.
The Apollo MVP4 controller coupled with VIA
’
s highly integrated south bridge, the VT82C686A, is ideal for high performance,
energy efficient, and highly integrated computer systems. The VT82C686A supports a PCI-to-ISA bus controller, four USB ports,
dual bus-master IDE with UltraDMA33/66, AC97 basic digital audio, system hardware monitoring, and integrated
“
Super-I/O
”
functionality.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VT8601 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Slot-1 / Socket-370 PCI North Bridge With Integrated AGP 2D / 3D Graphics Accelerator and Advanced Memory Controller |
| VT86C100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI FAST ETHERNET CONTROLLER |
| VT86C926 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AMAZON PCI ETHERNET CONTROLLER |
| VT8N1 | 制造商:PERKINELMER 制造商全稱:PerkinElmer Optoelectronics 功能描述:Photoconductive Cells and Analog Optoisolators (Vactrols) |
| VT8N2 | 制造商:PERKINELMER 制造商全稱:PerkinElmer Optoelectronics 功能描述:Photoconductive Cells and Analog Optoisolators (Vactrols) |
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