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VT82C693
Preliminary Revision 0.3
December 9, 1998
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Overview
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write buffers to minimize PCI master read latency and DRAM utilization. Delay transaction and read caching mechanisms are also
implemented for further improvement of overall system performance.
The 324-pin Ball Grid Array VT82C596A PCI to ISA bridge supports four levels (doublewords) of line buffers, type F DMA
transfers and delay transaction to allow efficient PCI bus utilization and (PCI-2.1 compliant). The VT82C596A also includes an
integrated keyboard controller with PS2 mouse support, integrated DS12885 style real time clock with extended 256 byte CMOS
RAM, integrated master mode enhanced IDE controller with full scatter / gather capability and extension to UltraDMA-33 / ATA-
33 for 33MB/sec transfer rate, integrated USB interface with root hub and two function ports with built-in physical layer
transceivers, Distributed DMA support, and OnNow / ACPI compliant advanced configuration and power management interface.
For sophisticated notebook implementations, the Apollo Pro-Plus provides independent clock stop control for the CPU / SDRAM,
PCI, and AGP buses and Dynamic CKE control for powering down of the SDRAM. A separate suspend-well plane is implemented
for the SDRAM control signals for Suspend-to-DRAM operation. Coupled with the VT82C596A south bridge chip, a complete
notebook PC main board can be implemented with no external TTLs.
The Apollo Pro-Plus chipset is ideal for high performance, high quality, high energy efficient and high integration desktop and
notebook AGP / PCI / ISA computer systems.