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參數(shù)資料
| 型號： | vt82c693 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | APOLLO PRO-PLUS |
| 中文描述： | 阿波羅專業(yè)普樂士 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大小： | 124K |
| 代理商： | VT82C693 |
VT82C693
Preliminary Revision 0.3
December 9, 1998
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3-
Features
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Advanced High-Performance DRAM Controller
DRAM interface synchronous with host CPU (66/100 MHz) or AGP (66MHz) for most flexible configuration
Concurrent CPU, AGP, and PCI access
Supports FP, EDO, SDRAM and VCM SDRAM memory types
Different DRAM types may be used in mixed combinations
Different DRAM timing for each bank
Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems
Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs
8 banks up to 1GB DRAMs (128Mb DRAM technology)
Flexible row and column addresses
64-bit data width only
3.3V DRAM interface with 5V-tolerant inputs
Programmable I/O drive capability for MA, command, and MD signals
Dual copies of MA signals for improved drive
Optional bank-by-bank ECC (single-bit error correction and multi-bit error detection)
or EC (error checking only) for DRAM integrity
Two-bank interleaving for 16Mbit SDRAM support
Two-bank and four bank interleaving for 64Mbit SDRAM support
Supports maximum 8-bank interleave (i.e., 8 pages open simultaneously); banks are allocated based on LRU
Independent SDRAM control for each bank
Seamless DRAM command scheduling for maximum DRAM bus utilization
(e.g., precharge other banks while accessing the current bank)
Four cache lines (16 quadwords) of CPU to DRAM write buffers
Four cache lines of CPU to DRAM read prefetch buffers
Read around write capability for non-stalled CPU read
Speculative DRAM read before snoop result
Burst read and write operation
x-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM from CPU or from DRAM controller
x-1-1-1-1-1-1-1 back-to-back accesses for SDRAM
BIOS shadow at 16KB increment
Decoupled and burst DRAM refresh with staggered RAS timing
CAS before RAS or self refresh
Mobile System Support
Dynamic power down of SDRAM (CKE)
Independent clock stop controls for CPU / SDRAM, AGP, and PCI bus
PCI and AGP bus clock run and clock generator control
VTT suspend power plane preserves memory data
Suspend-to-DRAM and Self-Refresh operation
EDO self-refresh and SDRAM self-refresh power down
8 bytes of BIOS scratch registers
Low-leakage I/O pads
Built-in NAND-tree pin scan test capability
3.3V, 0.35um, high speed / low power CMOS process
35 x 35 mm, 492 pin BGA Package
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