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參數(shù)資料
| 型號(hào)： | VT82885 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Real Time Clock |
| 中文描述： | 實(shí)時(shí)時(shí)鐘 |
| 文件頁(yè)數(shù)： | 12/16頁(yè) |
| 文件大小： | 72K |
| 代理商： | VT82885 |
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12
VT82885
Real Time Clock
VIA Technologies, Inc.
Pulse Width, DS/E High or
RD/WR# Low
PW
EH
125
ns
Input Rise and Fall Time
t
R
, t
F
t
RWH
t
RWS
30
ns
R/W# Hold Time
10
ns
R/W# Setup Time
before DS/E
50
ns
Chip Select Setup Time
before DS, WR#, or RD#
t
CS
20
ns
Chip Select Hold Time
t
CH
t
DHR
t
DHW
t
ASL
0
ns
Read Data Hold Time
10
80
ns
Write Data Hold Time
0
Muxed Address Valid Time
to AS/ALE Fall
30
ns
Muxed Address Hold Time
t
AHL
t
ASD
10
ns
Delay Time DS/E
to AS/ALE Rise
25
ns
Pulse Width AS/ALE High
PW
ASH
t
ASED
60
ns
Delay Time, AS/alE
to DS/E Rise
40
ns
Output Data Delay Time
from DS/E or RD#
t
DDR
20
120
ns
DataSetup Time
t
DSW
t
RWL
100
ns
Reset Pulse Width
5
μ
s
IRQ# Release from DS
t
IRDS
2
μ
s
IRQ# Release from
RESET#
t
IRR
2
μ
s
Delay Time before Update
Cycle
t
BUC
244
μ
s
Periodic Interrupt Time
Interval
t
PI
See Table
1
Time of Update Cycle
t
UC
1708
μ
s
NOTES
1.
All voltages are referenced to ground.
2.
All outputs are open.
3.
Applies to the AD0-AD7 pins, the IRQ#
pin and the SQW pin when each is in the
high impedence state.
4.
The IRQ# pin is open drain.
5.
Measured with a load as shown in
Figure 4.
FIGURE 4: OUTPUT LOAD
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