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參數(shù)資料
| 型號(hào)： | VSC830 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | 2.7Gb/s Asynchronous Dual 2x2 Crosspoint Switch |
| 中文描述： | 2.7Gb / s的異步雙2x2交叉點(diǎn)開關(guān) |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 195K |
| 代理商： | VSC830 |
VITESSE
Data Sheet
VSC830
Dual 2x2 Crosspoint Switch
2.7Gb/s Asynchronous
G52192-0, Rev 4.0
05/23/01
Page 12
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Design Guide
Introduction
The purpose of this document is to make it easier for system designers to use the VSC830 2.7Gb/s dual 2x2
crosspoint switch. This guide provides guidelines for I/O terminations, power supply decoupling and board lay-
out.
Signal Terminations
The high-speed inputs (A1A+/-, A1B+/-, A2A+/- and A2B+/-) on the VSC830 are internally terminated
with a programmable 100
termination between the true and complement input. The input termination can be
disabled by connecting the TERM_ENABLE pin to VEE. High impedance internal biasing resistors provide the
correct bias voltage at the inputs for AC-coupled applications (Figure 5).
Figure 5: High-Speed Input Termination
V
CC
= 3.3 V
V
EE
= GND
2.0 V
2.0 V
R
| |
= 3.15k
(approx.)
C
IN
Chip Boundary
Z
O
C
IN
TYP = 0.1
μ
F (capacitor value is selected for data input = 2.7Gb/s)
V
TT
= V
CC
- 1.3V
C
IN
Z
O
V
CC
= 3.3 V
V
EE
= GND
2.0 V
2.0 V
R
| |
= 3.15 k
(approx.)
C
IN
Chip Boundary
Z
O
R
T
= Z
O
C
IN
V
TT
V
TT
100
a) Termination Enabled
b) Termination Disabled
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