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參數(shù)資料
| 型號： | VSC8132QR |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.488Gb/s 1:32 SONET/SDH Demux |
| 中文描述： | MUX/DEMUX, PQFP128 |
| 封裝： | 14 X 20 MM, 2 MM HEIGHT, HEAT SINK, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 121K |
| 代理商： | VSC8132QR |
VITESSE
Preliminary Data Sheet
VSC8132
2.488Gb/s 1:32 SONET/SDH Demux
Page 4
G52250-0, Rev 3.1
12/7/00
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is
recommended that the V
CC
power supply be decoupled using a 0.1
μ
F and 0.01
μ
F capacitor placed in parallel
on each V
CC
power supply pin as close to the package as possible. If room permits, a 0.001
μ
F capacitor should
also be placed in parallel with the 0.1
μ
F and 0.01
μ
F capacitors mentioned above. Recommended capacitors are
low-inductance ceramic SMT X7R devices. For the 0.1
μ
F capacitor, a 0603 package should be used. The
0.01
μ
F and 0.001
μ
F capacitors can be either 0603 or 0402 packages.
For low frequency decoupling, 47
μ
F tantalum, low-inductance SMT caps should be sprinkled over the
board
’
s main +3.3V power supply and placed close to the C-L-C pi filter.
If the device is being used in an ECL environment with a -3.3V supply, all references to decoupling V
CC
must be changed to V
EE
, and all references to decoupling 3.3V must be changed to -3.3V.
AC Characteristics
Figure 2: Output Timing
Figure 3: Data Output Timing
78MHz CLK
78MHz DATA
SYNC PULSE
PARITY
t
PD1
t
PD2
D31
D0
MSB
LSB
Time
DI+
Differential Serial Data Input
CLKI+
Differential Clock Input
NOTE: Bit 31 (MSB) is received first, Bit 0 (LSB) is received last.
t
SERSU
t
SERHO
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