- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359431 > VSC8132QR (VITESSE SEMICONDUCTOR CORP) 2.488Gb/s 1:32 SONET/SDH Demux PDF資料下載
參數(shù)資料
| 型號： | VSC8132QR |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 2.488Gb/s 1:32 SONET/SDH Demux |
| 中文描述： | MUX/DEMUX, PQFP128 |
| 封裝： | 14 X 20 MM, 2 MM HEIGHT, HEAT SINK, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大小： | 121K |
| 代理商： | VSC8132QR |
VITESSE
Preliminary Data Sheet
VSC8132
2.488Gb/s 1:32 SONET/SDH Demux
Page 2
G52250-0, Rev 3.1
12/7/00
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Functional Description
High-Speed Clock and Data Interface
The incoming high-speed data and high-speed clock are received by high-speed inputs DI+ and CLKI+.
The inputs are internally biased to accommodate AC-coupling.
The data and clock inputs are internally terminated by a center-tapped resistor network. For differential
input DC-coupling, the network is terminated to the appropriate termination voltage,
V
TERM
providing a 50
to
V
TERM
termination for both true and complement inputs. For differential input AC-coupling, the network is ter-
minated to
V
TERM
via a blocking capacitor.
In most situations, these inputs will have high transition density and little DC offset. However, in cases
where this does not hold, direct DC connection is possible. All serial data and clock inputs have the same circuit
topology as shown in Figure 1. The reference voltage is created by a resistor divider as shown. If the input sig-
nal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be cen-
tered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DC-
coupling operations, it is recommended that the user provides an external reference voltage which has better
temperature and power supply noise rejection than the on-chip resistor divider. The external reference should
have a nominal value equivalent to the common mode switch point of the DC-coupled signal, and can be con-
nected to either side of the differential gate.
Figure 1: High-Speed Clock and Data Inputs
I
I
V
CC
= 3.3V
V
EE
= 0V
V
TERM
C
100nF
C
100nF
Z
0
Z
0
C
100nF
Chip Boundary
50
50
3k
3k
3k
3k
1.65V
1.65V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VSC8140 | 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8140QR | 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8140TW | 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8141 | Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8142 | 2.5G Multi-rate SONET/SDH Transceiver Family |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSC8140 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8140QR | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8140TW | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8141 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8141QR | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。