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參數(shù)資料
| 型號(hào)： | VSC8124 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Target Specification |
| 中文描述： | CLOCK RECOVERY CIRCUIT, PQFP100 |
| 封裝： | 14 X 14 MM, TQFP-100 |
| 文件頁(yè)數(shù)： | 4/20頁(yè) |
| 文件大?。?/td> | 652K |
| 代理商： | VSC8124 |
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VITESSE
2.488 Gb/s Quad
Data Re-timer
Target Specification
VSC8124
Page 4
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
2/23/00
G52271-0, Rev. 1.14
Figure 2: Re-timed Serial Output Data Eye Diagram
Table 2: Serial Output Data Specification
NOTES: 1) Jitter generation is measured at worst case power supply and temperature using 155.52 MHz clean reference clock
and clean serial data.
2) Jitter generation and rise, fall time specifications do not apply in re-timer bypass mode.
Parameter
Description
Min
Typ
Max
Units
Conditions
J
G
Jitter generation
-
-
12ps rms
15 ps rms
Normal Operation
J
G
Jitter generation
-
-
Fast Lock Mode
Within 40
μ
s after
REFCK phase
change
20 to 80%
J
G
Jitter generation
-
-
14ps rms
t
r
, t
f
Rise time, fall time
-
-
140
ps
Period
J
G
80%
20%
t
r
t
f
,
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| VSC8131 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator |
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