參數(shù)資料
型號(hào)： VSC8124
廠商： VITESSE SEMICONDUCTOR CORP
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： Target Specification
中文描述： CLOCK RECOVERY CIRCUIT, PQFP100
封裝： 14 X 14 MM, TQFP-100
文件頁(yè)數(shù)： 3/20頁(yè)
文件大小： 652K
代理商： VSC8124
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 3
2/23/00
VITESSE
Target Specification
VSC8124
2.488 Gb/s Quad
Data Re-timer
G52271-0, Rev. 1.14
Functional Description
Reference Clock
A clean reference clock should be provided to meet jitter specifications. An arbitrary discontinuity in refer-
ence clock phase can be tolerated without data error at slightly reduced jitter tolerance. (See Table 1) Phase
changes must not occur more often than every 20
μ
s. Serial data transition density must average
period. Two reference clock input ports are provided. The REFSEL pin selects the active port. When REFSEL
is not driven, it floats low, selecting REFCK0. Changing REFSEL implies a phase change.
Clock Recovery
The incoming serial data on each channel is presented to a clock recovery and data re-timing circuit. For
each channel, a phase detector and low pass filter force a local clock to track the average phase of the incoming
serial data. The low pass filter is first order to prevent jitter peaking in cascaded devices.
for that
Figure 1: Serial Input Data Eye Diagram
Table 1: Serial Input Data Specification
NOTE: 1) Jitter tolerance is measured at worst case power supply and temperature, using 155.52 MHz clean reference clock
(REFCK to meet 2.0 ps RMS jitter at less than 10 Mhz in bandwidth), and 600mV swing differential PRBS data
with150ps maximum rise time.
2) Jitter tolerance and re-timed data jitter are degraded in FASTLOCK mode.
3) Reference clock frequency tolerance:
f
<=
100 ppm
4) Jitter tolerance specifications do not apply in re-timer bypass mode.
Parameter
Description
Min
Typ
Max
Units
Conditions
J
T
J
T
Jitter tolerance
Jitter tolerance
220
150
-
-
-
ps
ps
Normal Operation
Fast Lock Mode
Within 20
μ
s after
REFCLK phase
change
170
J
T
Jitter tolerance
190
210
-
ps
Period
-
401.88
-
ps
0.5
≥
J
T
Eye Opening
Period
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參數(shù)描述
VSC8131 制造商:VITESSE 制造商全稱(chēng):Vitesse Semiconductor Corporation 功能描述:2.488 Gbit/sec 32:1 SONET/SDH Mux with Clock Generator
VSC8132 制造商:VITESSE 制造商全稱(chēng):Vitesse Semiconductor Corporation 功能描述:2.488Gb/s 1:32 SONET/SDH Demux
VSC8132QR 制造商:VITESSE 制造商全稱(chēng):Vitesse Semiconductor Corporation 功能描述:2.488Gb/s 1:32 SONET/SDH Demux
VSC8140 制造商:VITESSE 制造商全稱(chēng):Vitesse Semiconductor Corporation 功能描述:2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
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