參數(shù)資料
型號(hào)： VSC8116
廠商： Vitesse Semiconductor Corporation.
英文描述： ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation
中文描述： 自動(dòng)柜員機(jī)/ SONET / SDH的622/155Mb/s收發(fā)器復(fù)用/集成時(shí)鐘發(fā)生器解復(fù)用
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 358K
代理商： VSC8116
VITESSE
Data Sheet
VSC8116
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Page 4
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
G52220-0, Rev 4.1
1/8/00
PLL clock multiplier. Optics have either a PECL or TTL output, usually called “SD” (Signal Detect) or “FLAG”
indicating either a lack of or presence of optical power. Depending on the optics manufacture this signal is
either active high or active low polarity. If the optics Signal Detect or FLAG output is a “TTL” signal, it should
be connected to LOSTTL. If it’s a “PECL” signal it should be connected through a “PECL” to “TTL” translator
(such as the Motorola “MC100ELT21”) which then drives LOSTTL. The follow on part to VSC8116 is the
VSC8117, in this device the signal LOSTTL has been changed to LOSPECL, a PECL input.
Facility Loopback
The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set
high, the Facility Loopback mode is activated and the high speed serial receive data (RXDATAIN) is presented
at the high speed transmit output (TXDATAOUT). See Figure 3. In Facility Loopback mode the high speed
receive data (RXDATAIN) is also converted to parallel data and presented at the low speed receive data output
pins (RXOUT [7:0]). The receive clock (RXCLKIN) is also divided down and presented at the low speed clock
output (RXLSCKOUT).
Figure 3: Facility Loopback Data Path
Equipment Loopback
The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is
set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the paral-
lel to serial conversion of the low speed data (TXIN [7:0]) is selected and converted back to parallel data in the
receiver section and presented at the low speed parallel outputs (RXOUT [7:0]). See Figure 4. The internally
generated 155MHz/622MHz clock is used to generate the low speed receive clock output (RXLSCKOUT). In
Equipment Loopback mode the transmit data (TXIN [7:0]) is serialized and presented at the high speed output
(TXDATAOUT).
D
Q
D
Q
S1:8
Parallel
Q
D
RXDATAIN
TXDATAOUT
RXOUT[7:0]
Q
D
TXIN[7:0]
P8:1
Serial
PLL
0
1
FACLOOP
RXCLKIN
0
1
RXLSCKOUT
÷
8
相關(guān)PDF資料
PDF描述
VSC8116QP1 ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation
VSC8116QP2 ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation
VSC8117 ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
VSC8117QP GIGATRUE 550 CAT PATCH CBL SNAGLSS 20FT BL 25 PK
VSC8117QP1 GIGATRUE 550 CAT6 PATCH 25 FT, SNAGLESS, BLUE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VSC8116QP 制造商:VITESSE 制造商全稱(chēng):Vitesse Semiconductor Corporation 功能描述:ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation
VSC8116QP1 制造商:VITESSE 制造商全稱(chēng):Vitesse Semiconductor Corporation 功能描述:ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation
VSC8116QP2 制造商:VITESSE 制造商全稱(chēng):Vitesse Semiconductor Corporation 功能描述:ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation
VSC8117 制造商:VITESSE 制造商全稱(chēng):Vitesse Semiconductor Corporation 功能描述:ATM/SONET/SDH 622/155 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery
VSC8117QP 制造商:Vitesse Semiconductor Corporation 功能描述:Telecomm/Datacomm, Other
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