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參數(shù)資料
| 型號(hào)： | VSC8116 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation |
| 中文描述： | 自動(dòng)柜員機(jī)/ SONET / SDH的622/155Mb/s收發(fā)器復(fù)用/集成時(shí)鐘發(fā)生器解復(fù)用 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 358K |
| 代理商： | VSC8116 |
VITESSE
Data Sheet
VSC8116
ATM/SONET/SDH 622/155Mb/s Transceiver
Mux/Demux with Integrated Clock Generation
Page 18
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
G52220-0, Rev 4.1
1/8/00
Application Notes
AC Coupling and Terminating High-speed PECL I/Os
The high speed signals on the VSC8116 (RXDATAIN, RXCLKIN, TXDATAOUT, TXCLKOUT) use 3.3V
PECL levels which are essentially ECL levels shifted positive by 3.3 volts. The PECL I/Os are referenced to the
V
DD
supply (VDD) and are terminated to ground. Since most optics modules use either ECL or 5.0V PECL lev-
els, the high speed ports need to be either AC-coupled to overcome the difference in dc levels, or DC translated
(DC level shift).
The PECL receiver inputs of the VSC8116 are internally biased at VDD/2. Therefore, AC-coupling to the
VSC8116 inputs is accomplished by providing the pull-down resistor for the open-source PECL output and an
AC-coupling capacitor used to eliminate the DC component of the output signal. This capacitor allows the
PECL receivers of the VSC8116 to self-bias via its internal resistor divider network (see Figure 12).
The PECL output drivers are capable of sourcing current but not sinking it. To establish a LOW output
level, a pull-down resistor, traditionally connected to VDD-2.0V, is needed when the output FET is turned off.
Since VDD-2.0V is usually not present in the system, the resistor should be terminated to ground for conve-
nience. The VSC8116 output drivers should be either AC-coupled to the 5.0V PECL inputs of the optics mod-
ule, or translated (DC level shift). Appropriate biasing techniques for setting the DC-level of these inputs should
be employed.
The DC biasing and 50 ohm termination requirements can easily be integrated together using a thevenin
equivalent circuit as shown in Figure 11. The figure shows the appropriate termination values when interfacing
3.3V PECL to 5.0V PECL. This network provides the equivalent 50 ohm termination for the high speed I/Os
and also provides the required dc biasing for the receivers of the optics module. Table 15 contains recommended
values for each of the components.
Figure 11: AC Coupled High Speed I/O
PC Board Trace
PC Board Trace
DRIVER
(Optics Module)
RECEIVER
(Optics Module)
VSC8111
PECL I/O
R2
R4
C2
C1
R3
Note: Only one side of a differential signal is shown.
R1
GND
+3.3V
+5.0V
GND
GND
GND
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