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參數(shù)資料
| 型號(hào)： | VSC8114 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery |
| 中文描述： | 自動(dòng)柜員機(jī)/ SONET / SDH的622 Mb / s的集成時(shí)鐘發(fā)生器和時(shí)鐘恢復(fù)器/解復(fù)用器 |
| 文件頁數(shù)： | 2/24頁 |
| 文件大小： | 434K |
| 代理商： | VSC8114 |
VITESSE
Data Sheet
VSC8114
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Page 2
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
G52185-0, Rev 4.0
11/1/99
detector circuit which is used to provide frame pluses during the A1, A2 boundary in the serial to parallel con-
verter. This only occurs when OOF is high. Both internal and external LOS functions are supported.
The VSC8114 provides the parity error detection and generation for the 8 bit data bus. On the receive side,
the parity of the 8 bit data outputs is generated. On the transmit side, the parity of the 8 bit data input is calcu-
lated and compared with the received parity input.
VSC8114 Block Diagram
Transmit Section
Byte-wide data is presented to TXIN[7:0] and is clocked into the part on the rising edge of TXLSCKIN.
See Figure 1. The data is then serialized (MSB leading) and presented to the TXDATAOUT+/- pins. The serial
output stream is synchronized to the CMU generated clock which is a phase locked and frequency scaled ver-
D Q
0
1
0
1
D
Q
0
1
0
1
8
RXOUT[7:0]
RXOUTP
RXLSCKOUT
TXPERR
FP
OOF
EQULOOP
TXDATAOUT+/-
8
TXIN[7:0]
TXLSCKOUT
TXLSCKIN
FACLOOP
CMU
Divide-by-8
1:8
DEMUX
FRAMER
Divide-by-8
8:1
MUX
Parity/
REG
CRU
RXDATAIN+/-
RXCLKIN+/-
DSBLCRU
0
1
0
1
1
0
losdet
REFCLKP+/-
LOSDETEN_
REC-DATA
REC-CLK
REFSEL
Parity Chk
REG
TXINP
LOSTTL
LOSPECL
0
1
LOOPTIM0
1
0
CRUREFSEL
CRUREFCLK
0
1
CRUEQLP
RESET
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| VSC8115YA1 | STS-12/STS-3 Multi Rate Clock and Data Recovery Unit |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSC8114QB | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery |
| VSC8114QB1 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery |
| VSC8114QB2 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery |
| VSC8115 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:STS-12/STS-3 Multi Rate Clock and Data Recovery Unit |
| VSC8115XYA-05-T | 功能描述:IC CLOCK/DATA RECOVERY 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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