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參數(shù)資料
| 型號(hào)： | V827316K04S |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 2.5 VOLT 16M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE |
| 中文描述： | 2.5伏特16米x 72高性能無緩沖ECC DDR SDRAM內(nèi)存模塊 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 271K |
| 代理商： | V827316K04S |
MOSEL VITELIC
V827316K04S
9
V827316K04S Rev. 1.6 March 2002
AC Characteristics (cont.)
Notes:
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
DQS-Out edge to Data-Out edge Skew
t
DQSQ
-
0.5
-
0.5
-
0.6
ns
Data-Out hold time from DQS
t
QH
t
HPmin
-0.75ns
-
t
HPmin
-0.75ns
-
t
HPmin
-0.75ns
-
ns
1
Clock Half Period
t
HP
t
CH/L
min
-
t
CH/L
min
-
t
CH/L
min
-
ns
1
Input Setup Time (fast slew rate)
t
IS
0.9
-
0.9
-
1.1
-
ns
2,3,5,6
Input Hold Time (fast slew rate)
t
IH
0.9
-
0.9
-
1.1
-
ns
2,3,5,6
Input Setup Time (slow slew rate)
t
IS
1.0
-
1.0
-
1.1
-
ns
2,4,5,6
Input Hold Time (slow slew rate)
t
IH
1.0
-
1.0
-
1.1
-
ns
2,4,5,6
Input Pulse Width
t
IPW
2.2
-
2.2
-
-
-
ns
6
Write DQS High Level Width
t
DQSH
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Write DQS Low Level Width
t
DQSL
0.4
0.6
0.4
0.6
0.4
0.6
CLK
CLK to First Rising edge of DQS-In
t
DQSS
0.75
1.25
0.75
1.25
0.75
1.25
CLK
Data-In Setup Time to DQS-In (DQ & DM)
t
DS
0.5
-
0.5
-
0.6
-
ns
7
Data-in Hold Time to DQS-In (DQ & DM)
t
DH
0.5
-
0.5
-
0.6
-
ns
7
DQ & DM Input Pulse Width
t
DIPW
1.75
-
1.75
-
2
-
ns
Read DQS Preamble Time
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
CLK
Read DQS Postamble Time
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Write DQS Preamble Setup Time
t
WPRES
0
-
0
-
0
-
CLK
Write DQS Preamble Hold Time
t
WPREH
0.25
-
0.25
-
0.25
-
CLK
Write DQS Postamble Time
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Mode Register Set Delay
t
MRD
2
-
2
-
2
-
CLK
Power Down Exit Time
t
PDEX
10
-
10
-
10
-
ns
Exit Self Refresh to Non-Read Command
t
XSNR
75
-
75
-
80
-
ns
Exit Self Refresh to Read Command
t
XSRD
200
-
200
-
200
-
CLK
8
Average Periodic Refresh Interval
t
REFI
-
15.6
-
15.6
-
15.6
us
Parameter
Symbol
(PC1600)
(PC2100B)
(PC2100A)
Unit Note
Min
Max
Min
Max
Min
Max
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