參數(shù)資料
型號: V827316K04S
廠商: Mosel Vitelic, Corp.
英文描述: 2.5 VOLT 16M x 72 HIGH PERFORMANCE UNBUFFERED ECC DDR SDRAM MODULE
中文描述: 2.5伏特16米x 72高性能無緩沖ECC DDR SDRAM內(nèi)存模塊
文件頁數(shù): 5/13頁
文件大小: 271K
代理商: V827316K04S
MOSEL VITELIC
V827316K04S
5
V827316K04S Rev. 1.6 March 2002
29
Minimum RAS to CAS delay(=t
RCD
)
20ns
20ns
18ns
50h
50h
48h
30
Minimum active to precharge time(=t
RAS
)
50ns
45ns
45ns
32h
2Dh
2Dh
31
Module ROW density
128MB
20h
32
Command and address signal input setup time
1.1ns
0.9ns
0.9ns
B0h
90h
90h
33
Command and address signal input hold time
1.1ns
0.9ns
0.9ns
B0h
90h
90h
34
Data signal input setup time
0.6ns
0.5ns
0.5ns
60h
50h
50h
35
Data signal input hold time
0.6ns
0.5ns
0.5ns
60h
50h
50h
36-40
Superset information (may be used in future)
-
00h
41
SDRAM device minimum active to active/auto-refresh time
(=t
RC
)
70ns
65ns
60ns
46h
41h
3Ch
42
SDRAM device minimum active to autorefresh to active/auto-refresh
time (=t
RFC
)
80ns
75ns
67ns
50h
4Bh
43h
43
SDRAM device maximum device cycle time (=t
CK MAX
)
12ns
12ns
12ns
30h
30h
30h
44
SDRAM device maximum skew between DQS and DQ signals
(=t
DQSQ
)
0.6ns
0.5ns
0.5ns
3Ch
32h
32h
45
SDRAM device maximum read datahold skew factor (=t
QHS
)
1ns
0.75ns 0.75ns
A0h
75h
75h
46-61
Superset information (may be used in future)
-
00h
62
SPD data revision code
Initial release
00h
63
Checksum for Bytes 0 ~ 62
-
D6h
1Ch
BBh
64
Manufacturer JEDEC ID code
Mosel Vitelic
40h
65 -71
....... Manufacturer JEDEC ID code
Mosel Vitelic
40h
72
Manufacturing location
01h
73-90
Module part number (ASCII)
V827316K04S
91
Manufacturer revison code (For PCB)
0
00
92
Manufacturer revison code (For component)
0
00
93
Manufacturing date (Week)
-
-
94
Manufacturing date (Year)
-
-
95~98
Assembly serial #
-
-
99~127 Manufacturer specific data (may be used in future)
Undefined
00h
128~255 Open for customer use
Undefined
00h
Byte #
Function described
Function Supported
Hex value
A1
B0
B1
A1
B0
B1
Serial Presence Detect Information (cont.)
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