參數(shù)資料
型號(hào): V826664G24S
廠商: Mosel Vitelic, Corp.
英文描述: 512 MB 200-PIN DDR UNBUFFERED SODIMM 2.5 VOLT 64M x 64
中文描述: 512 MB的200 - pin的DDR SODIMM內(nèi)存2.5伏的緩沖6400 × 64
文件頁數(shù): 9/14頁
文件大?。?/td> 199K
代理商: V826664G24S
MOSEL VITELIC
V826664G24S
9
V826664G24S Rev. 1.0 August 2002
DDR SDRAM I
DD
SPEC TABLE
* Module I
DD
was calculated on the basis of component I
DD
and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Symbol
C0
DDR333@CL=2.5
B1
DDR266@CL=2
B0
DDR266@CL=2.5
A1
DDR200@CL=2
Unit
Notes
Typical
Typical
Typical
Typical
IDD0
880
800
800
640
mA
IDD1
1120
1000
1000
800
mA
IDD2P
450
380
380
260
mA
IDD2F
365
360
360
320
mA
IDD2Q
340
280
280
240
mA
IDD3P
450
380
380
260
mA
IDD3N
460
400
400
320
mA
IDD4R
1360
1360
1360
1120
mA
IDD4W
1680
1480
1480
1200
mA
IDD5
1600
1480
1480
1200
mA
IDD6
Normal
54
54
54
54
mA
Low power
30
30
30
30
mA
Optional
IDD7A
2800
2600
2600
2120
mA
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