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參數(shù)資料
| 型號： | V55C3256164VBLG10IPC |
| 廠商： | PROMOS TECHNOLOGIES INC |
| 元件分類： | DRAM |
| 英文描述： | SYNCHRONOUS DRAM, PBGA54 |
| 封裝： | ROHS COMPLIANT, MO-210, FBGA-54 |
| 文件頁數(shù)： | 7/46頁 |
| 文件大?。?/td> | 575K |
| 代理商： | V55C3256164VBLG10IPC |
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15
V55C3256164VB Rev. 1.0 March 2008
ProMOS TECHNOLOGIES
V55C3256164VB
Notes for AC Parameters:
1.
For proper power-up see the operation section of this data sheet.
2.
AC timing tests are referenced to the 0.9V crossover point for VCCQ=1.8V components. The transition time is mea-
sured between VIH and VIL. All AC measurements assume tT = 1ns with the AC output load circuit shown in
Figure 1.
4.
If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter.
5.
If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
6.
These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
7.
Referenced to the time which the output achieves the open circuit condition, not to output voltage levels
Read Cycle
21
tOH
Data Out Hold Time
3
–
3
–
ns
2
22
tLZ
Data Out to Low Impedance Time
1
–
1
–
ns
23
tHZ
Data Out to High Impedance Time
3
7
3
7
ns
7
24
tDQZ
DQM Data Out Disable Latency
–
2
–
2
CLK
Write Cycle
25
tWR
Write Recovery Time
1
–
1
–
CLK
26
tDQW
DQM Write Mask Latency
0
–
0
–
CLK
#
Symbol Parameter
Limit Values
Unit
Note
-7
-10
Min.
Max.
Min.
Max.
1.4V
tCS
tCH
tAC
tLZ
tOH
tHZ
CLK
COMMAND
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
VIH
VIL
tT
Figure 1.
tCK
AC Characteristics (Cont’d)
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