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參數(shù)資料
| 型號： | V53C8128HK45 |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 128K X 8 EDO DRAM, 45 ns, PDSO24 |
| 封裝： | 0.300 INCH, SOJ-26/24 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 222K |
| 代理商： | V53C8128HK45 |
6
MOSEL-VITELIC
V53C8128H
V53C8128H Rev. 1.1 November 1997
27
tWL1CL2
tWCS
Write Command Setup Time
0000
ns
12, 13
28
tCL1WH1
tWCH
Write Command Hold Time
5567
ns
29
tWL1WH1
tWP
Write Pulse Width
5567
ns
30
tRL1WH1
tWCR
Write Command Hold Time
28
30
35
40
ns
from
RAS
31
tWL1RH1
tRWL
Write Command to
RAS
12
13
14
ns
Lead Time
32
tDVWL2
tDS
Data in Setup Time
0000
ns
14
33
tWL1DX
tDH
Data in Hold Time
4567
ns
14
34
tWL1GL2
tWOH
Write to
OE Hold Time
5678
ns
14
35
tGH2DX
tOED
OE to Data Delay Time
5678
ns
14
36
tRL2RL2
tRWC
Read-Modify-Write
105
110
115
130
ns
(RMW)
Cycle Time
37
tRL1RH1
tRRW
Read-Modify-Write Cycle
70
75
80
87
ns
(RMW)
RAS Pulse Width
38
tCL1WL2
tCWD
CAS to WE Delay
28
30
32
34
ns
12
39
tRL1WL2
tRWD
RAS to WE Delay in
54
58
62
68
ns
12
Read-Modify-Write Cycle
40
tCL1CH1
tCRW
CAS Pulse Width (RMW)
46
48
50
52
ns
41
tAVWL2
tAWD
Col. Address to
WE Delay
35
38
41
42
ns
12
42
tCL2CL2
tPC
EDO Page Mode
14
15
17
19
ns
Read or Write Cycle Time
43
tCH2CL2
tCP
CAS Precharge Time
4567
ns
44
tAVRH1
tCAR
Column Address to
RAS
18
20
22
24
ns
Setup Time
45
tCH2QV
tCAP
Access Time from
21
23
25
27
ns
7
Column Precharge
46
tRL1DX
tDHR
Data in Hold Time
28
30
35
40
ns
Referenced to
RAS
47
tCL1RL2
tCSR
CAS Setup Time
10
ns
CAS-before-RAS Refresh
48
tRH2CL2
tRPC
RAS to CAS Precharge Time
0000
ns
49
tRL1CH1
tCHR
CAS Hold Time
8
10
12
ns
CAS-before-RAS Refresh
50
tCL2CL2
tPCM
EDO Page Mode Read-
58
60
65
70
ns
(RMW)
Modify-Write Cycle Time
AC Characteristics (continued)
35
40
45
50
#
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
Notes
JEDEC
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