參數(shù)資料
型號： USS-820D
英文描述： USS-820D USB Device Controller
中文描述： 號- 820D USB設(shè)備控制器
文件頁數(shù)： 3/58頁
文件大?。?/td> 868K
代理商： USS-820D
Data Sheet, Rev. 4
June 2001
Agere Systems Inc.
3
USB Device Controller
USS-820D
Description
5-8121
Figure 1. Block Diagram
USB
XCVR
FIFO
SIE
PROTOCOL
LAYER
EXTERNAL
MICROPROCESSOR
BUS
DPLS
DMNS
V
SS
V
DD
CONTROL
DIGITAL
PLL
FIFOs
USS-820D
OSCILLATOR
PLL
USS-820D is a USB device controller that provides a
programmable bridge between the USB and a local
microprocessor bus. It is available in two package
types: 44-pin MQFP (USS-820D) and 48-pin TQFP
(USS-820TD, formerly USS-825). The USS-820D
allows PC peripherals to upgrade to USB connectivity
without major redesign effort. It is programmable
through a simple read/write register interface that is
compatible with industry-standard USB microcontrol-
lers.
USS-820D is designed in 100% compliance with the
USB industry standard, allowing device-side USB prod-
ucts to be reliably installed using low-cost, off-the-shelf
cables and connectors.
The integrated USB transceiver supports 12 Mbits/s
full-speed operation. FIFO options support all four
transfer types: control, interrupt, bulk, and isochronous,
as described in
Universal Serial Bus Specification
Revision 1.1,
with a wide range of packet sizes. Its
double sets of FIFO enable the dual-packet mode
feature. The dual-packet mode feature reduces latency
by allowing simultaneous transfers on the host and
microprocessor sides of a given unidirectional
endpoint.
The USS-820D supports a maximum of eight bidirec-
tional endpoints with 16 FIFOs (eight for transmit and
eight for receive) associated with them. The FIFOs are
on-chip, and sizes are programmable up to a total of
1120 logical bytes. When the dual-packet mode feature
is enabled, the device uses a maximum of 2240 bytes
of physical storage. This additional physical FIFO stor-
age is managed by the device hardware and is trans-
parent to the user.
The FIFO sizes supported are 8 bytes, 16 bytes,
32 bytes, and 64 bytes for nonisochronous pipes, and
64 bytes, 256 bytes, 512 bytes, and 1024 bytes for iso-
chronous pipes. The FIFO size of a given endpoint
defines the upper limit to maximum packet size that the
hardware can support for that endpoint. This flexibility
covers a wide range of data rates, data types, and
combinations of applications.
The USS-820D can be clocked either by connecting a
12 MHz crystal to the XTAL1 and XTAL2 pins, or by
using a 12 MHz external oscillator. The internal 12 MHz
clock period, which is a function of either of these clock
sources, is referred to as the device clock period (t
CLK
)
throughout this data sheet.
Serial Interface Engine
The SIE is the USB protocol interpreter. It serves as a
communicator between the USS-820D and the host
through the USB lines.
The SIE functions include the following:
I
Package protocol sequencing.
I
SOP (start of packet), EOP (end of packet),
RESUME, and RESET signal detection and genera-
tion.
I
NRZI data encoding/decoding and bit stuffing.
I
CRC generation and checking for token and data.
I
Serial-to-parallel and parallel-to-serial data conver-
sion.
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參數(shù)描述
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USS-820FD 制造商:AGERE 制造商全稱:AGERE 功能描述:USB Device Controller
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