參數(shù)資料
型號: USB1T11AMX
廠商: Fairchild Semiconductor
文件頁數(shù): 7/10頁
文件大?。?/td> 0K
描述: IC TXRX SERIAL BUS UNIV 14SOIC
標(biāo)準(zhǔn)包裝: 1
類型: 收發(fā)器
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: USB 1.1
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 14-SOIC
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1223 (CN2011-ZH PDF)
其它名稱: USB1T11AMXDKR
1999 Fairchild Semiconductor Corporation
www.fairchildsemi.com
USB1T11A Rev. 1.0.4
6
U
S
B
1
T11A
U
n
iversal
Serial
B
u
s
Transceiver
AC Electrical Characteristics D+/D- Pins, Full Speed
Over recommended range of supply voltage and operating free air temperature unless otherwise noted.
VCC = 3.0V to 3.6V, CL = 50Pf; RL = kΩ on D+ to VCC.
Symbol
Parameter
Conditions
TA=-40 to +85°C
Units
Min.
Typ.
Max.
Driver Characteristics
tR, tF
Rise and Fall Time
10 and 90%, Figure 4
4
20
ns
tRFM
Rise/Fall Time Matching
tR / tF
90
110
%
VCRS
Output Signal Crossover Voltage
1.3
2.0
V
Driver Timings
tPLH
Driver Propagation Delay
(VPO,VMO/FSEO to D+/D-)
Figure 4
18
ns
tPHZ, tPLZ
Driver Disable Delay (/OE to D+/D-)
Figure 6
13
ns
tPZH, tPZL
Driver Enable Delay (/OE to D+/D-)
Figure 6
17
ns
Receiver Timings
tPLH
Receiver Propagation Delay
Figure 5
16
ns
tPHL
D+/D- to RVC
Figure 5
19
ns
tPLH, tPHL
Single-ended Receiver Delay
(D+/D- to VP, VM)
Figure 5
8
ns
AC Electrical Characteristics D+/D- Pins, Low Speed
Over recommended range of supply voltage and operating free air temperature unless otherwise noted.
VCC = 3.0V to 3.6V, CL = 200pF to 600pF; RL = 1.5kΩ on D- to VCC.
Symbol
Parameter
Conditions
TA=-40 to +85°C
Units
Min.
Typ.
Max.
Driver Characteristics
tLR, tLF
Rise and Fall Time
10 and 90%, Figure 4
75
300
ns
tRFM
Rise/Fall Time Matching
tR / tF
80
120
%
VCRS
Output Signal Crossover Voltage
1.3
2.0
V
Driver Timings
tPLH, tPHL
Driver Propagation Delay
(VPO,VMO/FSEO to D+/D-)
Figure 4
300
ns
tPHZ, tPLZ
Driver Disable Delay (/OE to D+/D-)
Figure 6
13
ns
tPZH, tPZL
Driver Enable Delay (/OE to D+/D-)
Figure 6
205
ns
Receiver Timings
tPLH, tPHL
Receiver Propagation Delay
(D+/D- to RVC)
Figure 5
18
ns
tPLH, tPHL
Single-ended Receiver Delay
(D+/D- to VP, VM)
Figure 5
28
ns
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