參數(shù)資料
型號: UPD78F9212GR-JJG-A
廠商: Renesas Electronics America
文件頁數(shù): 56/175頁
文件大?。?/td> 0K
描述: MCU 8BIT 4KB FLASH MEM 16-SSOP
標(biāo)準(zhǔn)包裝: 1
系列: 78K0S/Kx1+
核心處理器: 78K0S
芯體尺寸: 8-位
速度: 10MHz
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 4KB(4K x 8)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 16-SSOP(0.173",4.40mm 寬)
包裝: 托盤
其它名稱: 972-1046
UPD78F9212GR-JJG-A-ND
CHAPTER 8 WATCHDOG TIMER
User’s Manual U16994EJ6V0UD
147
Table 8-2. Option Byte Setting and Watchdog Timer Operation Mode
Option Byte Setting
Low-Speed Internal Oscillator Cannot Be Stopped Low-Speed Internal Oscillator Can Be Stopped by Software
Watchdog timer clock
source
Fixed to fRL
Note 1.
Selectable by software (fX, fRL or stopped)
When reset is released: fRL
Operation after reset
Operation starts with the maximum interval (2
18/fRL). Operation starts with the maximum interval
(2
18/fRL).
Operation mode
selection
The interval can be changed only once.
The clock selection/interval can be changed only
once.
Features
The watchdog timer cannot be stopped.
The watchdog timer can be stopped
Note 2.
Notes 1. As long as power is being supplied, low-speed internal oscillator cannot be stopped (except in the reset
period).
2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock
source of the watchdog timer.
<1> If the clock source is fX, clock supply to the watchdog timer is stopped under the following conditions.
When fX is stopped
In HALT/STOP mode
During oscillation stabilization time
<2> If the clock source is fRL, clock supply to the watchdog timer is stopped under the following conditions.
If the CPU clock is fX and if fRL is stopped by software before execution of the STOP instruction
In HALT/STOP mode
Remarks 1. fRL: Low-speed internal oscillation clock oscillation frequency
2. fX: System clock oscillation frequency
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