參數(shù)資料
型號(hào)： UPD784908GF
廠商： NEC Corp.
英文描述： 16-BIT SINGLE-CHIP MICROCONTROLLER
中文描述： 16位單片機(jī)
文件頁(yè)數(shù)： 41/98頁(yè)
文件大?。?/td> 657K
代理商： UPD784908GF
μ
PD784907, 784908
41
Data Sheet U11680EJ2V0DS00
8.5 Watch Timer
As the count clock, either of two types of clock can be input to the watch timer: the main clock (6.29 MHz/12.58
MHz) or the watch clock (32.768 kHz). They can be selected using the control register. The watch clock is input to
the watch timer only. It is not input to the CPU or other peripheral circuits. Therefore, the speed of CPU operation
cannot be slowed by the watch clock.
The watch timer generates interrupt signals (INTW), at 0.5-second intervals
Note
, by dividing the count clock. At
the same time, the watch timer sets the interrupt request flag (WIF) (where WIF refers to bit 7 of the interrupt control
register (WIC)).
By switching modes, the INTW generation interval can be changed to about 1 ms (fast-forward mode: normal
operation speed
×
512).
When the main clock is selected as the count clock, the watch timer stops if in STOP or IDLE standby mode, but
continues operating if in HALT standby mode. When the watch clock is selected as the count clock, the watch timer
continues operating regardless of the standby mode. The operation of the watch clock oscillator is controlled by means
of the watch timer mode register (WM).
The watch timer of the
μ
PD784908 does not have a buzzer output function.
Note
After the operation is enabled, the time until first INTW generation is not 0.5 s.
Table 8-3. Relationship between Count Clock and Watch Timer Operation
Count Clock Selection
Normal Operation Mode
Standby Modes
HALT mode
STOP mode
IDLE mode
Main clock
Operable
Operable
Stopped
Stopped
Watch clock
Operable
Operable
Operable
Operable
The watch timer consists of a frequency divider which divides the count clock by 3 and a counter which divides
the frequency output from the frequency divider by 2
14
. As the count clock, select the signal obtained by dividing the
internal system clock by 128 or that output by the watch clock oscillator.
Figure 8-7. Watch Timer Block Diagram
ON/OFF
WM.7
WM.6
0
1
0
1
0
1
SEL
SEL
SEL
1 2
3 4
5
6
7 8 9
10 11 1213
14
WM.2
INTW
STBC.7
WM.3
Reset
Main clock
f
XX
/128
Division
by 3
Counter
Counter
Watch
clock
oscillator
Main clock selection: 6.29 MHz
12.58 MHz
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