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μ
PD784907, 784908
75
Data Sheet U11680EJ2V0DS00
AC Characteristics (T
A
= –40 to +85
°
C, V
DD
= AV
DD
= 3.5 to 5.5 V, AV
SS
= V
SS
= 0 V)
(1) Read/write operation
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB
↓
)
t
SAST
V
DD
= 5.0 V
(0.5 + a)T – 11
29
ns
ASTB high-level width
t
WSTH
V
DD
= 5.0 V
(0.5 + a)T – 17
23
ns
Address hold time (from ASTB
↓
)
t
HSTLA
V
DD
= 5.0 V
0.5T – 19
21
ns
Address hold time (from RD
↑
)
t
HRA
V
DD
= 5.0 V
0.5T – 14
26
ns
Delay from address to RD
↓
t
DAR
V
DD
= 5.0 V
(1 + a)T – 5
74
ns
Address float time (from RD
↓
)
t
FRA
0
ns
Data input time from address
t
DAID
V
DD
= 5.0 V
(2.5 + a + n)T – 37
400
ns
Data input time from
ASTB
↓
t
DSTID
V
DD
= 5.0 V
(2 + n)T – 35
283
ns
Data input time from RD
↓
t
DRID
V
DD
= 5.0 V
(1.5 + n)T – 40
238
ns
Delay from ASTB
↓
to RD
↓
t
DSTR
V
DD
= 5.0 V
0.5T – 9
31
ns
Data hold time (from RD
↑
)
t
HRID
0
ns
Address active time from RD
↑
t
DRA
V
DD
= 5.0 V
0.5T – 2
38
ns
Delay from RD
↑
to ASTB
↑
t
DRST
V
DD
= 5.0 V
0.5T – 9
31
ns
RD low-level width
t
WRL
V
DD
= 5.0 V
(1.5 + n)T – 25
94
ns
Delay from address
↓
to WR
↓
t
DAW
V
DD
= 5.0 V
(1 + a)T – 5
74
ns
Address hold time (from WR
↑
)
t
HWA
V
DD
= 5.0 V
0.5T – 14
26
ns
Delay from ASTB
↓
to data output
t
DSTOD
V
DD
= 5.0 V
0.5T + 15
55
ns
Delay from WR
↓
to data output
t
DWOD
15
ns
Delay from ASTB
↓
to WR
↓
t
DSTW
V
DD
= 5.0 V
0.5T – 9
31
ns
Data setup time (to WR
↑
)
t
SODWR
V
DD
= 5.0 V
(1.5 + n)T – 20
99
ns
Data hold time (from WR
↑
)
t
HWOD
V
DD
= 5.0 V
0.5T – 14
26
ns
Delay from WR
↑
to ASTB
↑
t
DWST
V
DD
= 5.0 V
0.5T – 9
31
ns
WR low-level width
t
WWL
V
DD
= 5.0 V
(1.5 + n)T – 25
94
ns
Remark
T:
a:
n:
t
CYK
(system clock cycle time) V
DD
= 5.0 V T = 79 ns (MIN.)
1 during address wait, otherwise, 0
number of wait states (n
≥
0)