![](http://datasheet.mmic.net.cn/370000/UPD784907_datasheet_16743927/UPD784907_50.png)
μ
PD784907, 784908
50
Data Sheet U11680EJ2V0DS00
8.12 Simplified IEBus Controller
A newly developed IEBus controller is incorporated into the
μ
PD784908. This IEBus controller has fewer functions
than the IEBus interface function of previous product (incorporated into the 78K/0).
Table 8-5 compares the previous product and the new, simplified IEBus interface.
Table 8-5. Comparisons between Previous Product and Simplified IEBus Interface
Item
Previous Product (IEBus Incorporated into 78K/0)
Simplified IEBus
Communication mode
Modes 0 to 2
Fixed to mode 1
Internal system clock
6.0 (6.29) MHz
Internal buffer size
Transmission buffer 33 bytes (FIFO)
Reception buffer 40 bytes (FIFO)
Up to four frames can be received
Transmission/reception data register 1 byte
CPU processing
Processing before transmission start (data setting)
Setting and control of each communication status
Data write to the transmission buffer
Data read from the reception buffer
Processing before transmission start (data setting)
Setting and control of each communication status
Data write processing for every byte
Data read processing for every byte
Transmission control such as slave status
Control of multiple frames, remastering request
Hardware processing
Bit processing
(modulation/demodulation, error detection)
Field processing (generation, control)
Detection of arbitration results
Parity processing (generation, error detection)
ACK/NACK automatic response
Automatic data retransmitting
Automatic remastering
Transmission such as automatic slave status
Reception of multiple frames
Bit processing
(modulation/demodulation, error detection)
Field processing (generation, control)
Detection of arbitration results
Parity processing (generation, error detection)
ACK/NACK automatic response
Automatic data retransmitting