參數(shù)資料
型號(hào)： UPD784031GCA-3B9
廠商： NEC Corp.
英文描述： 16/8-BIT SINGLE-CHIP MICROCONTROLLER
中文描述： 16/8-BIT單片機(jī)
文件頁(yè)數(shù)： 65/90頁(yè)
文件大?。?/td> 377K
代理商： UPD784031GCA-3B9
μ
PD784031
65
(3) External wait timing
Remarks
T:
T
CYK
(system clock cycle time)
1 (during address wait), otherwise, 0
Number of wait states (n
≥
0)
a:
n:
(4) Refresh timing
Remark
T: T
CYK
(system clock cycle time)
Parameter
Delay from address to WAIT
↓
input
Delay from ASTB
↓
to WAIT
↓
input
Hold time from ASTB
↓
to WAIT
Delay from ASTB
↓
to WAIT
↑
Delay from RD
↓
to WAIT
↓
input
Hold time from RD
↓
to WAIT
↓
Delay from RD
↓
to WAIT
↑
Delay from WAIT
↑
to data input
Delay from WAIT
↑
to WR
↑
Delay from WAIT
↑
to RD
↑
Delay from WR
↓
to WAIT
↓
input
Hold time from WR
↓
to WAIT
Delay from WR
↓
to WAIT
↑
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
(0.5 + n) T + 5
(0.5 + n) T +10
nT + 5
nT + 10
0.5T
0.5T
nT + 5
nT + 10
MAX.
(2 + a) T - 40
(2 + a) T - 60
1.5T - 40
1.5T - 60
(1.5 + n) T - 40
(1.5 + n) T - 60
T - 50
T - 70
(1 + n) T - 40
(1 + n) T - 60
0.5T - 5
0.5T - 10
T - 50
T - 75
(1 + n) T - 40
(1 + n) T - 70
Conditions
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
Symbol
t
DAWT
t
DSTWT
t
HSTWTH
t
DSTWTH
t
DRWTL
t
HRWT
t
DRWTH
t
DWTID
t
DWTW
t
DWTR
t
DWWTL
t
HWWT
t
DWWTH
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Random read/write cycle time
REFRQ low-level pulse width
Delay from ASTB
↓
to REFRQ
Delay from RD
↑
to REFRQ
Delay from WR
↑
to REFRQ
Delay from REFRQ
↑
to ASTB
REFRQ high-level pulse width
MAX.
MIN.
3T
1.5T - 25
1.5T - 30
0.5T - 9
1.5T - 9
1.5T - 9
0.5T - 15
1.5T - 25
1.5T - 30
Symbol
t
RC
t
WRFQL
t
DSTRFQ
t
DRRFQ
t
DWRFQ
t
DRFQST
t
WRFQH
Conditions
V
DD
= +5.0 V
±
10 %
V
DD
= +5.0 V
±
10 %
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