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CHAPTER 14 SERIAL INTERFACE UART6
User’s Manual U16228EJ2V0UD
304
(4) Clock selection register 6 (CKSR6)
This register selects the base clock of serial interface UART6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Remark
CKSR6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 14-8. Format of Clock Selection Register 6 (CKSR6)
Address: FF56H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
CKSR6
0
0
0
0
TPS63
TPS62
TPS61
TPS60
TPS63
TPS62
TPS61
TPS60
Base clock (f
XCLK6
) selection
0
0
0
0
f
X
(10 MHz)
0
0
0
1
f
X
/2 (5 MHz)
0
0
1
0
f
X
/2
2
(2.5 MHz)
0
0
1
1
f
X
/2
3
(1.25 MHz)
0
1
0
0
f
X
/2
4
(625 kHz)
0
1
0
1
f
X
/2
5
(312.5 kHz)
0
1
1
0
f
X
/2
6
(156.25 kHz)
0
1
1
1
f
X
/2
7
(78.13 kHz)
1
0
0
0
f
X
/2
8
(39.06 kHz)
1
0
0
1
f
X
/2
9
(19.53 kHz)
1
0
1
0
f
X
/2
10
(9.77 kHz)
1
0
1
1
TM50 output
Note
Other than above
Setting prohibited
Note
To select the output of TM50 as the base clock, start the operation by setting 8-bit timer/event counter 50 so
that the duty is 50% of the output in the PWM mode (bit 6 (TMC506) of the TMC50 register = 1), and then
set TPS63, TPS62, TPS61, and TPS60 to 1, 0, 1, and 1, respectively. It is not necessary to enable the
TO50 pin as a timer output pin (bit 0 (TOE50) of the TMC register may be 0 or 1).
Cautions 1. When the Ring-OSC clock is selected as the clock to be supplied to the CPU, the clock of the
Ring-OSC oscillator is divided and supplied as the count clock. If the base clock is the Ring-
OSC clock, the operation of serial interface UART6 is not guaranteed.
2. Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1.
Figures in parentheses are for operation with f
X
= 10 MHz
2.
f
X
: X1 input clock oscillation frequency